GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

haswell: use tsc for udelay() 

Instead of using the local apic timer for udelay() use the tsc.
That way SMM, romstage, and ramstage all use the same delay
functionality.

Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3169
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2013-05-01 15:39:28 -05:00 committed by Ronald G. Minnich
parent 935850e082
commit 7cb1ba9a61
5 changed files with 36 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/intel/haswell/Kconfig
View File

@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS
def_bool y
select SMP
select SSE2
select UDELAY_LAPIC
select UDELAY_TSC
select TSC_CONSTANT_RATE
select SMM_TSEG
select SMM_MODULES
select RELOCATABLE_MODULES

3
src/cpu/intel/haswell/Makefile.inc
View File

@ -1,7 +1,9 @@
ramstage-y += haswell_init.c
subdirs-y += ../../x86/name
ramstage-y += mp_init.c
ramstage-y += tsc_freq.c
romstage-y += romstage.c
romstage-y += tsc_freq.c
ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc

31
src/cpu/intel/haswell/tsc_freq.c Normal file
View File

@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include "cpu/intel/haswell/haswell.h"
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
platform_info = rdmsr(MSR_PLATFORM_INFO);
return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff);
}

1
src/northbridge/intel/haswell/Makefile.inc
View File

@ -29,7 +29,6 @@ romstage-y += early_init.c
romstage-y += report_platform.c
romstage-y += ../../../arch/x86/lib/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
# We don't ship that, but booting without it is bound to fail

63
src/northbridge/intel/haswell/udelay.c
View File

@ -1,63 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2008 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <delay.h>
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
#include "cpu/intel/haswell/haswell.h"
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
{
tsc->lo = (a & 0xffff) * (b & 0xffff);
tsc->hi = ((tsc->lo >> 16)
+ ((a & 0xffff) * (b >> 16))
+ ((b & 0xffff) * (a >> 16)));
tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
}
void udelay(u32 us)
{
u32 dword;
tsc_t tsc, tsc1, tscd;
msr_t msr;
u32 divisor;
u32 d; /* ticks per us */
msr = rdmsr(MSR_PLATFORM_INFO);
divisor = (msr.lo >> 8) & 0xff;
d = HASWELL_BCLK * divisor;
multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo;
if ((dword < tsc1.lo) || (dword < tscd.lo)) {
tsc1.hi++;
}
tsc1.lo = dword;
tsc1.hi += tscd.hi;
do {
tsc = rdtsc();
} while ((tsc.hi < tsc1.hi)
|| ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
}