soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -7,6 +7,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <fsp/api.h>
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#include <fsp/fsp_debug_event.h>
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#include <fsp/ppi/mp_service_ppi.h>
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#include <fsp/util.h>
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#include <option.h>
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@ -509,6 +510,8 @@ static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
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static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
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const struct soc_intel_alderlake_config *config)
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{
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if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
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s_cfg->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)fsp_debug_event_handler);
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/* PCH UART selection for FSP Debug */
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s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
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ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
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@ -6,6 +6,7 @@
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#include <cpu/intel/cpu_ids.h>
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#include <device/device.h>
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#include <drivers/wifi/generic/wifi.h>
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#include <fsp/fsp_debug_event.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pcie_rp.h>
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@ -364,6 +365,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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{
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const struct soc_intel_alderlake_config *config;
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FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
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FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
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if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER))
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arch_upd->FspEventHandler = (UINT32)((FSP_EVENT_HANDLER *)
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fsp_debug_event_handler);
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config = config_of_soc();
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