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Disable AMD8111 USB2 and remove hard code addr in amd8111 IDE 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu 2004-05-05 18:03:42 +00:00
parent 52f851dd1d
commit 7ccff4ea0c
10 changed files with 27 additions and 21 deletions
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2
src/mainboard/tyan/s2850/Config.lb
View File

@ -170,7 +170,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy pnp 2e.0 on # Floppy

2
src/mainboard/tyan/s2875/Config.lb
View File

@ -169,7 +169,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy pnp 2e.0 on # Floppy

2
src/mainboard/tyan/s2880/Config.lb
View File

@ -159,7 +159,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy pnp 2e.0 off # Floppy

2
src/mainboard/tyan/s2881/Config.lb
View File

@ -169,7 +169,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy pnp 2e.0 on # Floppy

2
src/mainboard/tyan/s2882/Config.lb
View File

@ -174,7 +174,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy pnp 2e.0 on # Floppy

2
src/mainboard/tyan/s2885/Config.lb
View File

@ -172,7 +172,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 on # Floppy pnp 2e.0 on # Floppy

2
src/mainboard/tyan/s4880/Config.lb
View File

@ -165,7 +165,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy pnp 2e.0 off # Floppy

2
src/mainboard/tyan/s4882/Config.lb
View File

@ -169,7 +169,7 @@ northbridge amd/amdk8 "mc0"
pci 0:1.6 off pci 0:1.6 off
pci 1:0.0 on pci 1:0.0 on
pci 1:0.1 on pci 1:0.1 on
pci 1:0.2 on pci 1:0.2 off
pci 1:1.0 off pci 1:1.0 off
superio winbond/w83627hf link 1 superio winbond/w83627hf link 1
pnp 2e.0 off # Floppy pnp 2e.0 off # Floppy

14
src/southbridge/amd/amd8111/amd8111.c
View File

@ -11,6 +11,7 @@ void amd8111_enable(device_t dev)
device_t bus_dev; device_t bus_dev;
unsigned index; unsigned index;
uint16_t reg_old, reg; uint16_t reg_old, reg;
uint8_t byte;
/* See if we are on the behind the amd8111 pci bridge */ /* See if we are on the behind the amd8111 pci bridge */
bus_dev = dev->bus->dev; bus_dev = dev->bus->dev;
@ -38,6 +39,18 @@ void amd8111_enable(device_t dev)
return; return;
} }
} }
if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
(dev->device == PCI_DEVICE_ID_AMD_8111_USB2)) {
if(!dev->enabled) {
byte = pci_read_config8(lpc_dev, 0x47);
byte |= (1<<7);
pci_write_config8(lpc_dev, 0x47, byte);
return;
}
}
reg = reg_old = pci_read_config16(lpc_dev, 0x48); reg = reg_old = pci_read_config16(lpc_dev, 0x48);
reg &= ~(1 << index); reg &= ~(1 << index);
if (dev->enabled) { if (dev->enabled) {
@ -46,6 +59,7 @@ void amd8111_enable(device_t dev)
if (reg != reg_old) { if (reg != reg_old) {
pci_write_config16(lpc_dev, 0x48, reg); pci_write_config16(lpc_dev, 0x48, reg);
} }
} }
struct chip_control southbridge_amd_amd8111_control = { struct chip_control southbridge_amd_amd8111_control = {

18
src/southbridge/amd/amd8111/amd8111_ide.c
View File

@ -10,6 +10,7 @@ static void ide_init(struct device *dev)
/* Enable ide devices so the linux ide driver will work */ /* Enable ide devices so the linux ide driver will work */
uint16_t word; uint16_t word;
uint8_t byte;
int enable_a=1, enable_b=1; int enable_a=1, enable_b=1;
word = pci_read_config16(dev, 0x40); word = pci_read_config16(dev, 0x40);
@ -31,21 +32,12 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x40, word); pci_write_config16(dev, 0x40, word);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
word = 0x0f; word = 0x0f;
pci_write_config16(dev, 0x42, word); pci_write_config16(dev, 0x42, word);
/* The AMD768 has a bug where the BM DMA address must be
* 256 byte aligned while it is only 16 bytes long.
* Hard code this to a valid address below 0x1000
* where automatic port address assignment starts.
* FIXME: I assume the 8111 does the same thing. We should
* clarify. stepan@suse.de
*/
pci_write_config32(dev, 0x20, 0xf01);
pci_write_config32(dev, 0x48, 0x205e5e5e);
word = 0x06a;
pci_write_config16(dev, 0x4c, word);
} }
static struct device_operations ide_ops = { static struct device_operations ide_ops = {