soc/amd/picasso: move to using smbus_host.h definitions
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,27 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PICASSO_SMBUS_H__
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#define __PICASSO_SMBUS_H__
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#include <stdint.h>
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#include <soc/iomap.h>
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int do_smbus_read_byte(u32 mmio, u8 device, u8 address);
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int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val);
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int do_smbus_recv_byte(u32 mmio, u8 device);
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int do_smbus_send_byte(u32 mmio, u8 device, u8 val);
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#endif /* __PICASSO_SMBUS_H__ */
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@ -18,10 +18,10 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/smbus.h>
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#include <device/smbus_host.h>
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#include <cpu/x86/lapic.h>
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#include <arch/ioapic.h>
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#include <soc/southbridge.h>
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#include <soc/smbus.h>
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/*
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* The southbridge enables all USB controllers by default in SMBUS Control.
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@ -15,8 +15,8 @@
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#include <stdint.h>
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#include <console/console.h>
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#include <device/smbus_host.h>
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#include <amdblocks/acpimmio.h>
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#include <soc/smbus.h>
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#include <soc/southbridge.h>
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/*
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*/
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#define SMBUS_TIMEOUT (100 * 1000 * 10)
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static u8 controller_read8(u32 base, u8 reg)
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static u8 controller_read8(uintptr_t base, u8 reg)
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{
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switch (base) {
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case ACPIMMIO_SMBUS_BASE:
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@ -33,13 +33,13 @@ static u8 controller_read8(u32 base, u8 reg)
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case ACPIMMIO_ASF_BASE:
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return asf_read8(reg);
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default:
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printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n",
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printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n",
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base);
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}
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return 0xff;
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}
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static void controller_write8(u32 base, u8 reg, u8 val)
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static void controller_write8(uintptr_t base, u8 reg, u8 val)
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{
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switch (base) {
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case ACPIMMIO_SMBUS_BASE:
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asf_write8(reg, val);
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break;
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default:
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printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n",
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printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n",
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base);
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}
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}
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static int smbus_wait_until_ready(u32 mmio)
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static int smbus_wait_until_ready(uintptr_t mmio)
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{
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u32 loops;
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loops = SMBUS_TIMEOUT;
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return -2; /* time out */
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}
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static int smbus_wait_until_done(u32 mmio)
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static int smbus_wait_until_done(uintptr_t mmio)
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{
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u32 loops;
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loops = SMBUS_TIMEOUT;
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return -3; /* timeout */
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}
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int do_smbus_recv_byte(u32 mmio, u8 device)
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int do_smbus_recv_byte(uintptr_t mmio, u8 device)
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{
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u8 byte;
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return byte;
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}
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int do_smbus_send_byte(u32 mmio, u8 device, u8 val)
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int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val)
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{
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u8 byte;
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return 0;
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}
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int do_smbus_read_byte(u32 mmio, u8 device, u8 address)
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int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address)
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{
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u8 byte;
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return byte;
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}
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int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val)
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int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val)
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{
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u8 byte;
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@ -29,7 +29,6 @@
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#include <amdblocks/acpi.h>
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#include <soc/cpu.h>
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#include <soc/southbridge.h>
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#include <soc/smbus.h>
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#include <soc/smi.h>
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#include <soc/amd_pci_int_defs.h>
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#include <delay.h>
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