cpu/x86/smm: Promote smm_memory_map()
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -3,7 +3,6 @@ CONFIG_VENDOR_INTEL=y
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CONFIG_BOARD_INTEL_GALILEO=y
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# CONFIG_FSP_DEBUG_ALL is not set
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CONFIG_DISPLAY_MTRRS=y
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CONFIG_DISPLAY_SMM_MEMORY_MAP=y
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CONFIG_DISPLAY_ESRAM_LAYOUT=y
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CONFIG_BOOTBLOCK_NORMAL=y
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CONFIG_ON_DEVICE_ROM_LOAD=y
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@ -15,6 +15,7 @@
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#include <console/console.h>
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#include <cpu/intel/romstage.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <arch/symbols.h>
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#include <commonlib/helpers.h>
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#include <program_loading.h>
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@ -69,6 +70,9 @@ static void romstage_main(unsigned long bist)
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printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
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}
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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prepare_and_run_postcar(&early_mtrrs);
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/* We do not return here. */
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}
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@ -84,3 +84,23 @@ void __weak stage_cache_external_region(void **base, size_t *size)
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*size = 0;
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}
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}
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void smm_list_regions(void)
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{
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uintptr_t base;
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size_t size;
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int i;
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smm_region(&base, &size);
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if (!size)
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return;
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printk(BIOS_DEBUG, "SMM Memory Map\n");
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printk(BIOS_DEBUG, "SMRAM : 0x%zx 0x%zx\n", base, size);
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for (i = 0; i < SMM_SUBREGION_NUM; i++) {
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if (smm_subregion(i, &base, &size))
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continue;
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printk(BIOS_DEBUG, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
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}
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}
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@ -30,25 +30,6 @@ __weak void soc_after_silicon_init(void)
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{
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}
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/* Display SMM memory map */
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static void smm_memory_map(void)
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{
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uintptr_t base;
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size_t size;
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int i;
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printk(BIOS_SPEW, "SMM Memory Map\n");
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smm_region(&base, &size);
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printk(BIOS_SPEW, "SMRAM : 0x%zx 0x%zx\n", base, size);
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for (i = 0; i < SMM_SUBREGION_NUM; i++) {
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if (smm_subregion(i, &base, &size))
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continue;
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printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
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}
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}
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static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
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{
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const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
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@ -147,9 +128,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
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static void fsp_cache_save(struct prog *fsp)
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{
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if (CONFIG(DISPLAY_SMM_MEMORY_MAP))
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smm_memory_map();
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if (CONFIG(NO_STAGE_CACHE))
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return;
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@ -160,4 +160,7 @@ enum {
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* 0 on success, < 0 on failure. */
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int smm_subregion(int sub, uintptr_t *start, size_t *size);
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/* Print the SMM memory layout on console. */
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void smm_list_regions(void);
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#endif /* CPU_X86_SMM_H */
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@ -94,7 +94,6 @@ config FSP_DEBUG_ALL
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# Enable display and verification for coreboot build tests
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select DISPLAY_HOBS
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select DISPLAY_MTRRS
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select DISPLAY_SMM_MEMORY_MAP
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select DISPLAY_UPD_DATA
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select DISPLAY_ESRAM_LAYOUT
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select DISPLAY_FSP_CALLS_AND_STATUS
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@ -67,6 +67,9 @@ asmlinkage void car_stage_entry(void)
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if (romstage_handoff_init(s3_resume))
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printk(BIOS_ERR, "Failed to set romstage handoff data\n");
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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post_code(0x44);
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if (postcar_frame_init(&pcf, 1 * KiB))
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die("Unable to initialize postcar frame.\n");
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@ -152,6 +152,9 @@ asmlinkage void car_stage_entry(void)
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if (romstage_handoff_init(s3_resume))
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printk(BIOS_ERR, "Failed to set romstage handoff data\n");
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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post_code(0x44);
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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@ -22,6 +22,7 @@
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#include <console/console.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#if CONFIG(EC_GOOGLE_CHROMEEC)
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#include <ec/google/chromeec/ec.h>
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#endif
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@ -146,6 +147,9 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
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/* Call into mainboard. */
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mainboard_romstage_entry(&rp);
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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prepare_and_run_postcar(&early_mtrrs);
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/* We do not return here. */
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}
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@ -15,10 +15,6 @@ source "src/soc/intel/common/pch/Kconfig"
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comment "Intel SoC Common coreboot stages"
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source "src/soc/intel/common/basecode/Kconfig"
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config DISPLAY_SMM_MEMORY_MAP
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bool "SMM: Display the SMM memory map"
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default n
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config SOC_INTEL_COMMON_RESET
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bool
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default n
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@ -24,6 +24,7 @@
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#include <console/usb.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <timestamp.h>
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@ -255,9 +256,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
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romstage_handoff_init(prev_sleep_state == ACPI_S3);
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post_code(0x4f);
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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/* Load the ramstage. */
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post_code(0x4f);
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run_ramstage();
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while (1);
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}
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@ -22,6 +22,7 @@
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#include <console/console.h>
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#include <console/usb.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <timestamp.h>
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#include <version.h>
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@ -169,6 +170,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
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if (!CONFIG(FSP_MEMORY_DOWN))
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save_dimm_info();
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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/* Load the ramstage. */
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post_code(0x4e);
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run_ramstage();
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@ -31,6 +31,7 @@
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#include "southbridge/intel/fsp_rangeley/gpio.h"
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#include "southbridge/intel/fsp_rangeley/romstage.h"
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include "gpio.h"
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void main(FSP_INFO_HEADER *fsp_info_header)
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@ -121,9 +122,11 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
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*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
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post_code(0x4e);
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post_code(0x4f);
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if (CONFIG(SMM_TSEG))
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smm_list_regions();
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/* Load the ramstage. */
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post_code(0x4f);
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run_ramstage();
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while (1);
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}
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