fixes for epia.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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14e72218f3
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7cf52c979f
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@ -40,7 +40,9 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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*/
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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unsigned char c;
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c = smbus_read_byte(device, address);
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return c;
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}
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@ -57,15 +57,18 @@ static inline void smbus_delay(void)
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static int smbus_wait_until_ready(void)
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{
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unsigned char c;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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c = my_inb(smbus_io_base + SMBHSTSTAT);
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c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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while((c & 1) == 1) {
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printk_err("c is 0x%x\n", c);
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c = my_inb(smbus_io_base + SMBHSTSTAT);
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print_err("c is ");
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print_err_hex8(c);
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print_err("\n");
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c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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/* nop */
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}
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@ -75,13 +78,15 @@ static int smbus_wait_until_ready(void)
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void smbus_reset(void)
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{
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
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outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
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outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
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outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
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smbus_wait_until_ready();
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printk_err("After reset status %#x\n", my_inb(smbus_io_base + SMBHSTSTAT));
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print_err("After reset status ");
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print_err_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
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print_err("\n");
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}
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@ -89,12 +94,13 @@ void smbus_reset(void)
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static int smbus_wait_until_done(void)
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{
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unsigned long loops;
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unsigned char byte;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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byte = my_inb(smbus_io_base + SMBHSTSTAT);
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byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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if (byte & 1)
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break;
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@ -105,65 +111,64 @@ static int smbus_wait_until_done(void)
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static void smbus_print_error(unsigned char host_status_register)
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{
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printk_err("smbus_error: 0x%02x\n", host_status_register);
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print_err("smbus_error: ");
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print_err_hex8(host_status_register);
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print_err("\n");
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if (host_status_register & (1 << 4)) {
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printk_err("Interrup/SMI# was Failed Bus Transaction\n");
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print_err("Interrup/SMI# was Failed Bus Transaction\n");
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}
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if (host_status_register & (1 << 3)) {
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printk_err("Bus Error\n");
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print_err("Bus Error\n");
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}
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if (host_status_register & (1 << 2)) {
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printk_err("Device Error\n");
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print_err("Device Error\n");
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}
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if (host_status_register & (1 << 1)) {
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printk_err("Interrupt/SMI# was Successful Completion\n");
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print_err("Interrupt/SMI# was Successful Completion\n");
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}
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if (host_status_register & (1 << 0)) {
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printk_err("Host Busy\n");
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print_err("Host Busy\n");
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}
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}
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/* SMBus routines borrowed from VIA's Trident Driver */
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/* this works, so I am not going to touch it for now -- rgm */
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static unsigned char smbus_read(unsigned char devAdr, unsigned char bIndex,
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unsigned char *result)
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static unsigned char smbus_read_byte(unsigned char devAdr,
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unsigned char bIndex)
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{
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unsigned short i;
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unsigned char bData;
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unsigned char sts;
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/* clear host status */
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my_outb(0xff, smbus_io_base);
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outb(0xff, SMBUS_IO_BASE);
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/* check SMBUS ready */
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for ( i = 0; i < 0xFFFF; i++ )
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if ( (my_inb(smbus_io_base) & 0x01) == 0 )
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if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
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break;
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/* set host command */
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my_outb(bIndex, smbus_io_base+3);
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outb(bIndex, SMBUS_IO_BASE+3);
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/* set slave address */
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my_outb(devAdr | 0x01, smbus_io_base+4);
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outb(devAdr | 0x01, SMBUS_IO_BASE+4);
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/* start */
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my_outb(0x48, smbus_io_base+2);
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outb(0x48, SMBUS_IO_BASE+2);
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/* SMBUS Wait Ready */
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for ( i = 0; i < 0xFFFF; i++ )
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if ( ((sts = my_inb(smbus_io_base)) & 0x01) == 0 )
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if ( ((sts = inb(SMBUS_IO_BASE)) & 0x01) == 0 )
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break;
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if ((sts & ~3) != 0) {
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smbus_print_error(sts);
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return 0;
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}
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bData=my_inb(smbus_io_base+5);
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bData=inb(SMBUS_IO_BASE+5);
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*result = bData;
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/* return 1 if ok */
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return 1;
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return bData;
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}
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@ -182,35 +187,35 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
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/* setup transaction */
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/* disable interrupts */
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my_outb(my_inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
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outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
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/* set the device I'm talking too */
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my_outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
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outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
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/* set the command/address... */
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my_outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data read */
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my_outb((my_inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2),
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smbus_io_base + SMBHSTCTL);
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
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SMBUS_IO_BASE + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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my_outb(my_inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
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outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
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/* clear the data byte...*/
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my_outb(0, smbus_io_base + SMBHSTDAT0);
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outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
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/* start the command */
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my_outb((my_inb(smbus_io_base + SMBHSTCTL) | 0x40),
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smbus_io_base + SMBHSTCTL);
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outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
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SMBUS_IO_BASE + SMBHSTCTL);
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/* poll for transaction completion */
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smbus_wait_until_done();
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host_status_register = my_inb(smbus_io_base + SMBHSTSTAT);
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host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
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/* Ignore the In Use Status... */
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host_status_register &= ~(1 << 6);
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/* read results of transaction */
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byte = my_inb(smbus_io_base + SMBHSTDAT0);
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byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
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smbus_print_error(byte);
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*result = byte;
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