amd/stoneyridge: Add pci_dev macros
Add #defines that will allow easy use of PCI devices across stages. Future work can convert soc/amd/stoneyridge to use these and clean up the DEV_D18F4 macro still in place. Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Marshall Dawson
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@ -19,107 +19,132 @@
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#include <device/pci_def.h>
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#include <rules.h>
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#define _SOC_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func))
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#else
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#include <arch/io.h>
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#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func)
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#endif
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/* GNB Root Complex */
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#define GNB_DEV 0x0
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#define GNB_FUNC 0
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#define GNB_DEVID 0x1576
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#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
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#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC)
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/* IOMMU */
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#define IOMMU_DEV 0x0
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#define IOMMU_FUNC 2
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#define IOMMU_DEVID 0x1577
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#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
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#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC)
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/* Internal Graphics */
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#define GFX_DEV 0x1
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#define GFX_FUNC 0
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#define GFX_DEVID 098e4 /* subject to SKU/OPN variation */
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#define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC)
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#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC)
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/* HD Audio 0 */
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#define HDA0_DEV 0x1
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#define HDA0_FUNC 1
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#define HDA0_DEVID 015b3
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#define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
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#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC)
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/* Host Bridge */
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#define HOST_DEV 0x2
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#define HOST_FUNC 0
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#define HOST_DEVID 0x157b
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#define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC)
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#define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC)
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/* PCIe GPP Bridge 0 */
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#define PCIE0_DEV 0x2
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#define PCIE0_FUNC 1
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#define PCIE0_DEVID 0x157c
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#define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC)
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#define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC)
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/* PCIe GPP Bridge 1 */
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#define PCIE1_DEV 0x2
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#define PCIE1_FUNC 2
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#define PCIE1_DEVID 0x157c
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#define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC)
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#define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC)
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/* PCIe GPP Bridge 2 */
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#define PCIE2_DEV 0x2
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#define PCIE2_FUNC 3
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#define PCIE2_DEVID 0x157c
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#define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC)
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#define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC)
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/* PCIe GPP Bridge 3 */
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#define PCIE3_DEV 0x2
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#define PCIE3_FUNC 4
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#define PCIE3_DEVID 0x157c
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#define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC)
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#define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC)
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/* PCIe GPP Bridge 4 */
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#define PCIE4_DEV 0x2
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#define PCIE4_FUNC 5
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#define PCIE4_DEVID 0x157c
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#define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC)
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#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC)
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/* Platform Security Processor */
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#define PSP_DEV 0x8
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#define PSP_FUNC 0
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#define PSP_DEVID 0x1578
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#define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC)
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#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC)
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/* HD Audio 1 */
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#define HDA1_DEV 0x9
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#define HDA1_FUNC 2
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#define HDA1_DEVID 0x157a
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#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
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#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC)
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/* HT Configuration */
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#define HT_DEV 0x18
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#define HT_FUNC 0
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#define HT_DEVID 0x15b0
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#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC)
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#define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC)
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/* Address Maps */
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#define ADDR_DEV 0x18
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#define ADDR_FUNC 1
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#define ADDR_DEVID 0x15b1
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#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
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#define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC)
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/* DRAM Configuration */
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#define DCT_DEV 0x18
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#define DCT_FUNC 2
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#define DCT_DEVID 0x15b2
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#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC)
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#define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC)
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/* Misc. Configuration */
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#define MISC_DEV 0x18
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#define MISC_FUNC 3
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#define MISC_DEVID 0x15b3
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#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC)
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#define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC)
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/* PM Configuration */
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#define PM_DEV 0x18
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#define PM_FUNC 4
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#define PM_DEVID 0x15b4
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#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC)
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#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC)
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#if !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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#define DEV_D18F4 dev_find_slot(0, PM_DEVFN)
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@ -132,12 +157,14 @@
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#define NB_FUNC 5
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#define NB_DEVID 0x15b5
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#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC)
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#define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC)
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/* XHCI */
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#define XHCI_DEV 0x10
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#define XHCI_FUNC 0
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#define XHCI_DEVID 0x7914
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#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
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#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC)
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/* SATA */
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#define SATA_DEV 0x11
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@ -146,29 +173,34 @@
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#define AHCI_DEVID_MS 0x7901
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#define AHCI_DEVID_AMD 0x7904
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#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
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#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC)
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/* EHCI */
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#define EHCI_DEV 0x12
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#define EHCI_FUNC 0
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#define EHCI_DEVID 0x7908
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#define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC)
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#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC)
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/* SMBUS */
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#define SMBUS_DEV 0x14
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#define SMBUS_FUNC 0
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#define SMBUS_DEVID 0x790b
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#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
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#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
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/* LPC BUS */
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#define PCU_DEV 0x14
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#define LPC_FUNC 3
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#define LPC_DEVID 0x790e
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#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC)
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#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
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/* SD Controller */
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#define SD_DEV 0x14
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#define SD_FUNC 7
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#define SD_DEVID 0x7906
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#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC)
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#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC)
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#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */
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