AGESA: Use explicit PCI IO config access in bootblock
This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I994bb257db96300c2eb8872be6fae2a92bbabab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17531 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -34,15 +34,15 @@ static void hudson_enable_rom(void)
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dev = PCI_DEV(0, 0x14, 3);
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dev = PCI_DEV(0, 0x14, 3);
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/* Decode variable LPC ROM address ranges 1 and 2. */
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/* Decode variable LPC ROM address ranges 1 and 2. */
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reg8 = pci_read_config8(dev, 0x48);
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reg8 = pci_io_read_config8(dev, 0x48);
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reg8 |= (1 << 3) | (1 << 4);
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reg8 |= (1 << 3) | (1 << 4);
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pci_write_config8(dev, 0x48, reg8);
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pci_io_write_config8(dev, 0x48, reg8);
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/* LPC ROM address range 1: */
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/* LPC ROM address range 1: */
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/* Enable LPC ROM range mirroring start at 0x000e(0000). */
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/* Enable LPC ROM range mirroring start at 0x000e(0000). */
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pci_write_config16(dev, 0x68, 0x000e);
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pci_io_write_config16(dev, 0x68, 0x000e);
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/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
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/* Enable LPC ROM range mirroring end at 0x000f(ffff). */
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pci_write_config16(dev, 0x6a, 0x000f);
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pci_io_write_config16(dev, 0x6a, 0x000f);
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/* LPC ROM address range 2: */
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/* LPC ROM address range 2: */
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/*
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/*
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@ -52,9 +52,9 @@ static void hudson_enable_rom(void)
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* 0xffe0(0000): 2MB
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* 0xffe0(0000): 2MB
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* 0xffc0(0000): 4MB
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* 0xffc0(0000): 4MB
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*/
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*/
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pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
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pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
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/* Enable LPC ROM range end at 0xffff(ffff). */
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/* Enable LPC ROM range end at 0xffff(ffff). */
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pci_write_config16(dev, 0x6e, 0xffff);
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pci_io_write_config16(dev, 0x6e, 0xffff);
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}
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}
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static void bootblock_southbridge_init(void)
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static void bootblock_southbridge_init(void)
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