From 7d1a137b845ad0b4d1aa1553070b26411b899cf6 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 21 Oct 2020 10:42:25 +0800 Subject: [PATCH] mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons --- .../google/volteer/variants/baseboard/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 7486aef84c..b76f627873 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -103,10 +103,10 @@ chip soc/intel/tigerlake register "PcieClkSrcClkReq[1]" = "1" # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality - register "PcieClkSrcUsage[2]" = "0xFF" - register "PcieClkSrcUsage[4]" = "0xFF" - register "PcieClkSrcUsage[5]" = "0xFF" - register "PcieClkSrcUsage[6]" = "0xFF" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED" # Enable SATA register "SataEnable" = "1"