sb/amd/{cimx,sb{7,8}00}: Use PCI_DEVFN()
Change-Id: I731fd4ecfab679cd3d830a89bc82c56cf9008bc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS
Kyösti Mälkki
parent
e8b5c31f2c
commit
7d1a948fbb
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@ -347,11 +347,11 @@ static void sb900_enable(struct device *dev)
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//- commonInitEarlyPost(sb_config);
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switch (dev->path.pci.devfn) {
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case (0x10 << 3) | 0: /* 0:10:0 XHCI-USB */
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case PCI_DEVFN(0x10, 0): /* XHCI-USB */
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//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
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break;
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case (0x11 << 3) | 0: /* 0:11.0 SATA */
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case PCI_DEVFN(0x11, 0): /* SATA */
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if (dev->enabled) {
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sb_config->SATAMODE.SataMode.SataController = ENABLED;
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if (sb_chip->boot_switch_sata_ide == 1)
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@ -365,18 +365,18 @@ static void sb900_enable(struct device *dev)
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//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
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break;
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case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
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case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
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case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
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case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
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case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
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case PCI_DEVFN(0x12, 0): /* OHCI-USB1 */
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case PCI_DEVFN(0x12, 2): /* EHCI-USB1 */
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case PCI_DEVFN(0x13, 0): /* OHCI-USB2 */
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case PCI_DEVFN(0x13, 2): /* EHCI-USB2 */
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case PCI_DEVFN(0x14, 5): /* OHCI-USB4 */
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//- usbInitBeforePciEnum(sb_config); // USB POST TIME Only
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break;
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case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
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case PCI_DEVFN(0x14, 0): /* SMBUS */
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break;
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case (0x14 << 3) | 1: /* 0:14:1 IDE */
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case PCI_DEVFN(0x14, 1): /* IDE */
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if (dev->enabled) {
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sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
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} else {
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@ -385,7 +385,7 @@ static void sb900_enable(struct device *dev)
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//- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
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break;
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case (0x14 << 3) | 2: /* 0:14:2 HDA */
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case PCI_DEVFN(0x14, 2): /* HDA */
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if (dev->enabled) {
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if (sb_config->AzaliaController == AZALIA_DISABLE) {
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sb_config->AzaliaController = AZALIA_AUTO;
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@ -399,13 +399,13 @@ static void sb900_enable(struct device *dev)
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break;
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case (0x14 << 3) | 3: /* 0:14:3 LPC */
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case PCI_DEVFN(0x14, 3): /* LPC */
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break;
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case (0x14 << 3) | 4: /* 0:14:4 PCI */
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case PCI_DEVFN(0x14, 4): /* PCI */
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break;
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case (0x14 << 3) | 6: /* 0:14:6 GEC */
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case PCI_DEVFN(0x14, 6): /* GEC */
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if (dev->enabled) {
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sb_config->GecConfig = 0;
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printk(BIOS_DEBUG, "gec enabled\n");
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@ -416,10 +416,10 @@ static void sb900_enable(struct device *dev)
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//- gecInitBeforePciEnum(sb_config); // Init GEC
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break;
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case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
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case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
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case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
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case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
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case PCI_DEVFN(0x15, 0): /* PCIe PortA */
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case PCI_DEVFN(0x15, 1): /* PCIe PortB */
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case PCI_DEVFN(0x15, 2): /* PCIe PortC */
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case PCI_DEVFN(0x15, 3): /* PCIe PortD */
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gpp_port = (dev->path.pci.devfn) & 0x03;
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if (dev->enabled) {
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sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
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@ -167,53 +167,53 @@ void sb7xx_51xx_enable(struct device *dev)
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return;
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switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
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case (0x11 << 3) | 0:
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case PCI_DEVFN(0x11, 0):
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index = 8;
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set_sm_enable_bits(sm_dev, 0xac, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 3;
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break;
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case (0x12 << 3) | 0:
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case (0x12 << 3) | 1:
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case (0x12 << 3) | 2:
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case PCI_DEVFN(0x12, 0):
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case PCI_DEVFN(0x12, 1):
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case PCI_DEVFN(0x12, 2):
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index = dev->path.pci.devfn & 3;
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set_sm_enable_bits(sm_dev, 0x68, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 2;
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break;
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case (0x13 << 3) | 0:
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case (0x13 << 3) | 1:
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case (0x13 << 3) | 2:
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case PCI_DEVFN(0x13, 0):
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case PCI_DEVFN(0x13, 1):
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case PCI_DEVFN(0x13, 2):
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index = (dev->path.pci.devfn & 3) + 4;
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set_sm_enable_bits(sm_dev, 0x68, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 2;
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break;
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case (0x14 << 3) | 5:
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case PCI_DEVFN(0x14, 5):
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index = 7;
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set_sm_enable_bits(sm_dev, 0x68, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 2;
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break;
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case (0x14 << 3) | 0:
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case PCI_DEVFN(0x14, 0):
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index = 0;
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break;
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case (0x14 << 3) | 1:
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case PCI_DEVFN(0x14, 1):
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index = 1;
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break;
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case (0x14 << 3) | 2:
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case PCI_DEVFN(0x14, 2):
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index = 3;
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set_pmio_enable_bits(sm_dev, 0x59, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 4;
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break;
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case (0x14 << 3) | 3:
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case PCI_DEVFN(0x14, 3):
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index = 20;
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set_sm_enable_bits(sm_dev, 0x64, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 1;
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break;
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case (0x14 << 3) | 4:
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case PCI_DEVFN(0x14, 4):
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index = 4;
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break;
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default:
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@ -294,7 +294,7 @@ void sb800_enable(struct device *dev)
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printk(BIOS_DEBUG, "sb800_enable() 2\n");
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switch (dev->path.pci.devfn - (devfn - (0x14 << 3))) {
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case (0x11 << 3) | 0:
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case PCI_DEVFN(0x11, 0):
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index = 8;
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set_pmio_enable_bits(0xDA, 1 << 0,
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(dev->enabled ? 1 : 0) << 0);
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@ -307,63 +307,63 @@ void sb800_enable(struct device *dev)
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pci_write_config32(dev, 0x40, dword);//for (;;);
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index += 32 * 3;
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break;
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case (0x12 << 3) | 0:
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case (0x12 << 3) | 2:
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case PCI_DEVFN(0x12, 0):
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case PCI_DEVFN(0x12, 2):
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index = (dev->path.pci.devfn & 0x3) / 2;
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set_pmio_enable_bits(0xEF, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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break;
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case (0x13 << 3) | 0:
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case (0x13 << 3) | 2:
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case PCI_DEVFN(0x13, 0):
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case PCI_DEVFN(0x13, 2):
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index = (dev->path.pci.devfn & 0x3) / 2 + 2;
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set_pmio_enable_bits(0xEF, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 2;
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break;
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case (0x14 << 3) | 0:
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case PCI_DEVFN(0x14, 0):
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index = 0;
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break;
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case (0x14 << 3) | 1:
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case PCI_DEVFN(0x14, 1):
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index = 1;
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set_pmio_enable_bits(0xDA, 1 << 3,
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(dev->enabled ? 0 : 1) << 3);
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break;
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case (0x14 << 3) | 2:
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case PCI_DEVFN(0x14, 2):
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index = 0;
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set_pmio_enable_bits(0xEB, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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break;
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case (0x14 << 3) | 3:
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case PCI_DEVFN(0x14, 3):
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index = 0;
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set_pmio_enable_bits(0xEC, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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index += 32 * 1;
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break;
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case (0x14 << 3) | 4:
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case PCI_DEVFN(0x14, 4):
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index = 0;
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set_pmio_enable_bits(0xEA, 1 << index,
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(dev->enabled ? 0 : 1) << index);
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break;
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case (0x14 << 3) | 5:
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case PCI_DEVFN(0x14, 5):
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index = 6;
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set_pmio_enable_bits(0xEF, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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break;
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case (0x14 << 3) | 6:
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case PCI_DEVFN(0x14, 6):
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index = 0;
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set_pmio_enable_bits(0xF6, 1 << index,
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(dev->enabled ? 0 : 1) << index);
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break;
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case (0x15 << 3) | 0:
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case PCI_DEVFN(0x15, 0):
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set_sb800_gpp(dev);
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index = 4;
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break;
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case (0x15 << 3) | 1:
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case (0x15 << 3) | 2:
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case (0x15 << 3) | 3:
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case PCI_DEVFN(0x15, 1):
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case PCI_DEVFN(0x15, 2):
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case PCI_DEVFN(0x15, 3):
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break;
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case (0x16 << 3) | 0:
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case (0x16 << 3) | 2:
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case PCI_DEVFN(0x16, 0):
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case PCI_DEVFN(0x16, 2):
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index = (dev->path.pci.devfn & 0x3) / 2 + 4;
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set_pmio_enable_bits(0xEF, 1 << index,
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(dev->enabled ? 1 : 0) << index);
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