AGESA f14: Consolidate early P-states setting
Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -98,6 +98,10 @@ void amd_initmmio(void)
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LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
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MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
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LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
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/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
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MsrReg = 0;
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LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader);
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}
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void amd_initenv(void)
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@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
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*/
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -43,9 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr(0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -37,21 +37,9 @@
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/agesa/s3_resume.h>
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#define MSR_MTRR_VARIABLE_BASE6 0x020C
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#define MSR_MTRR_VARIABLE_MASK6 0x020D
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#define MSR_PSTATE_CONTROL 0xC0010062
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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msr_t msr;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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msr.lo = 0;
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msr.hi = 0;
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wrmsr (MSR_PSTATE_CONTROL, msr);
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amd_initmmio();
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@ -62,9 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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@ -51,9 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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u32 val;
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/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
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__writemsr (0xc0010062, 0);
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amd_initmmio();
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if (!cpu_init_detectedx && boot_cpu()) {
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