AGESA f14: Consolidate early P-states setting

Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-11-20 08:03:49 +02:00
parent 036a581b8f
commit 7d25651ed3
11 changed files with 4 additions and 40 deletions

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@ -98,6 +98,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
MsrReg = 0;
LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader);
}
void amd_initenv(void)

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@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
*/
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

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@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

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@ -43,9 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr(0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

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@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

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@ -37,21 +37,9 @@
#include <cpu/amd/mtrr.h>
#include <cpu/amd/agesa/s3_resume.h>
#define MSR_MTRR_VARIABLE_BASE6 0x020C
#define MSR_MTRR_VARIABLE_MASK6 0x020D
#define MSR_PSTATE_CONTROL 0xC0010062
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
msr_t msr;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
msr.lo = 0;
msr.hi = 0;
wrmsr (MSR_PSTATE_CONTROL, msr);
amd_initmmio();

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@ -62,9 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

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@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

View File

@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {

View File

@ -51,9 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
__writemsr (0xc0010062, 0);
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {