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AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT 

Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2013-12-22 20:48:40 +02:00
parent b316585eaf
commit 7d3045b517
5 changed files with 8 additions and 13 deletions
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3
src/cpu/amd/model_fxx/init_cpus.c
View File

@ -295,11 +295,12 @@ static u32 init_cpus(u32 cpu_init_detectedx)
} }
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
#if CONFIG_K8_REV_F_SUPPORT
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo, train_ram_on_node(id.nodeid, id.coreid, sysinfo,
(unsigned)STOP_CAR_AND_CPU); (unsigned)STOP_CAR_AND_CPU);
#endif #endif
#endif
STOP_CAR_AND_CPU(); STOP_CAR_AND_CPU();
} }

2
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@ -31,11 +31,13 @@
#if CONFIG_WAIT_BEFORE_CPUS_INIT #if CONFIG_WAIT_BEFORE_CPUS_INIT
void cpus_ready_for_init(void) void cpus_ready_for_init(void)
{ {
#if CONFIG_K8_REV_F_SUPPORT
#if CONFIG_MEM_TRAIN_SEQ == 1 #if CONFIG_MEM_TRAIN_SEQ == 1
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox)); struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - sizeof(*sysinfox));
// wait for ap memory to trained // wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox); wait_all_core0_mem_trained(sysinfox);
#endif #endif
#endif
} }
#endif #endif

4
src/mainboard/asus/a8n_e/Kconfig
View File

@ -31,10 +31,6 @@ config APIC_ID_OFFSET
hex hex
default 0x0 default 0x0
config MEM_TRAIN_SEQ
int
default 2
config SB_HT_CHAIN_ON_BUS0 config SB_HT_CHAIN_ON_BUS0
int int
default 2 default 2

4
src/mainboard/msi/ms7135/Kconfig
View File

@ -24,10 +24,6 @@ config APIC_ID_OFFSET
hex hex
default 0x0 default 0x0
config MEM_TRAIN_SEQ
int
default 2
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "MS-7135" default "MS-7135"

8
src/northbridge/amd/amdk8/Kconfig
View File

@ -41,10 +41,6 @@ config WAIT_BEFORE_CPUS_INIT
bool bool
default n default n
config MEM_TRAIN_SEQ
int
default 0
# Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and # Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and
# single DIMM is indeed unreliable without it). # single DIMM is indeed unreliable without it).
config K8_FORCE_2T_DRAM_TIMING config K8_FORCE_2T_DRAM_TIMING
@ -104,6 +100,10 @@ if DIMM_DDR2
endif endif
endif #DIMM_DDR2 endif #DIMM_DDR2
config MEM_TRAIN_SEQ
int
default 0
endif #K8_REV_F_SUPPORT endif #K8_REV_F_SUPPORT
config IOMMU config IOMMU