start of 970 port
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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#
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# Config file for IBM CPC925
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#
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config chip.h
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initobject cpc925.o
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initobject cpc925_pci.o
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object cpc925.o
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object cpc925_pci.o
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driver cpc925_northbridge.o
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struct northbridge_ibm_cpc925_config {
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/* Nothing yet */
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};
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extern struct chip_operations northbridge_ibm_cpc925_ops;
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#include <stdint.h>
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#include <arch/io.h>
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#include "cpc925.h"
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void cpc925_init(void);
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void sdram_init(void);
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void
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memory_init(void)
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{
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cpc925_init();
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sdram_init();
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cpc925_pci_init();
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}
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void
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cpc925_init(void)
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{
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}
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void
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sdram_init()
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{
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}
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#ifndef _CPC925_H_
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#define _CPC925_H_
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#endif
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include <cpu/cpu.h>
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#include "chip.h"
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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resource->base = 0;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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resource->base = 0x80000000ULL;
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resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void ram_resource(device_t dev, unsigned long index,
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unsigned long basek, unsigned long sizek)
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{
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struct resource *resource;
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if (!sizek) {
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return;
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}
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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int idx;
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 1024*1024); /* FIXME */
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/* And assign the resources */
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assign_resources(&dev->link[0]);
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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{
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max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = &pci_ppc_conf1,
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};
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static void cpu_bus_init(device_t dev)
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{
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initialize_cpus(&dev->link[0]);
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}
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static void cpu_bus_noop(device_t dev)
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{
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = cpu_bus_noop,
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.set_resources = cpu_bus_noop,
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.enable_resources = cpu_bus_noop,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
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dev->ops = &pci_domain_ops;
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}
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else if (dev->path.type == DEVICE_PATH_CPU_BUS) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_ibm_cpc925_ops = {
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CHIP_NAME("CPC925")
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.enable_dev = enable_dev,
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};
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#include <stdint.h>
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#include <arch/io.h>
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#include "cpc925.h"
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#include "cpc925_pci.h"
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void
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cpc925_pci_init(void)
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{
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}
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#ifndef _CPC925_PCI_H_
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#define _CPC925_PCI_H_
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#endif
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