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Fintek and Intel i3100 Super I/O cleanups. 

- Drop commented out "config chip.h" and a duplicate link to a datasheet.

 - F71805F -> F71805F/FG, to mention all variants.
 
 - Use u8/u16/ etc. everywhere.
 
 - Add a missing (C) line.
 
 - Fix up a bunch of pnp_dev_info[] structs according to the datasheets.
 
 - Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register
   pair on this Super I/O.
   
 - Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the
   respective code in superio.c. Also: Add missing LDNs to f71863fg.h.
   
 - i3100: Add some more comments and datasheet infos.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-11-05 00:07:13 +00:00
parent e4870474b9
commit 7d3418849d
16 changed files with 72 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/superio/fintek/f71805f/Makefile.inc
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@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_FINTEK_F71805F) += superio.c

4
src/superio/fintek/f71805f/f71805f.h
View File

@ -30,7 +30,7 @@
#define F71805F_FDC 0x00 /* Floppy */
#define F71805F_SP1 0x01 /* UART1 */
#define F71805F_SP2 0x02 /* UART2 */
#define F71805F_PP 0x03 /* Parallel Port */
#define F71805F_HWM 0x04 /* Hardware Monitor */
#define F71805F_PP 0x03 /* Parallel port */
#define F71805F_HWM 0x04 /* Hardware monitor */
#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */
#define F71805F_PME 0x0a /* Power Management Events (PME) */

8
src/superio/fintek/f71805f/f71805f_early_serial.c
View File

@ -23,19 +23,19 @@
#include <arch/romcc_io.h>
#include "f71805f.h"
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
u16 port = dev >> 8;
outb(0x87, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
u16 port = dev >> 8;
outb(0xaa, port);
}
static void f71805f_enable_serial(device_t dev, unsigned int iobase)
static void f71805f_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

4
src/superio/fintek/f71805f/superio.c
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@ -18,8 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Datasheet: http://www.fintek.com.tw/files/productfiles/F71805F_V025.pdf */
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
@ -107,6 +105,6 @@ static void enable_dev(device_t dev)
}
struct chip_operations superio_fintek_f71805f_ops = {
CHIP_NAME("Fintek F71805F Super I/O")
CHIP_NAME("Fintek F71805F/FG Super I/O")
.enable_dev = enable_dev
};

4
src/superio/fintek/f71859/Makefile.inc
View File

@ -1,6 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Marc Jones <marcj303@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
@ -16,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c

8
src/superio/fintek/f71859/f71859_early_serial.c
View File

@ -23,19 +23,19 @@
#include <arch/romcc_io.h>
#include "f71859.h"
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
u16 port = dev >> 8;
outb(0x87, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
u16 port = dev >> 8;
outb(0xaa, port);
}
static void f71859_enable_serial(device_t dev, unsigned int iobase)
static void f71859_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

1
src/superio/fintek/f71859/superio.c
View File

@ -19,7 +19,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>

4
src/superio/fintek/f71863fg/chip.h
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@ -18,13 +18,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <pc80/keyboard.h>
#include <device/device.h>
#include <uart8250.h>
/* This chip doesn't have keyboard and mouse support. */
extern struct chip_operations superio_fintek_f71863fg_ops;
struct superio_fintek_f71863fg_config {
struct uart8250 com1, com2;
struct pc_keyboard keyboard;
};

10
src/superio/fintek/f71863fg/f71863fg.h
View File

@ -22,8 +22,10 @@
#define F71863FG_FDC 0x00 /* Floppy */
#define F71863FG_SP1 0x01 /* UART1 */
#define F71863FG_SP2 0x02 /* UART2 */
#define F71863FG_PP 0x03 /* Parallel Port */
#define F71863FG_HWM 0x04 /* Hardware Monitor */
#define F71863FG_KBC 0x05 /* KBC devices */
#define F71863FG_PP 0x03 /* Parallel port */
#define F71863FG_HWM 0x04 /* Hardware monitor */
#define F71863FG_KBC 0x05 /* PS/2 keyboard and mouse */
#define F71863FG_GPIO 0x06 /* General Purpose I/O (GPIO) */
#define F71863FG_PME 0x0a /* Power Management Events (PME) */
#define F71863FG_VID 0x07 /* VID */
#define F71863FG_SPI 0x08 /* SPI */
#define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */

8
src/superio/fintek/f71863fg/f71863fg_early_serial.c
View File

@ -23,19 +23,19 @@
#include <arch/romcc_io.h>
#include "f71863fg.h"
static inline void pnp_enter_conf_state(device_t dev)
static void pnp_enter_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
u16 port = dev >> 8;
outb(0x87, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned int port = dev >> 8;
u16 port = dev >> 8;
outb(0xaa, port);
}
static void f71863fg_enable_serial(device_t dev, unsigned int iobase)
static void f71863fg_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);

16
src/superio/fintek/f71863fg/superio.c
View File

@ -18,7 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
@ -56,6 +55,10 @@ static void f71863fg_init(device_t dev)
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case F71863FG_KBC:
res0 = find_resource(dev, PNP_IDX_IO0);
pc_keyboard_init(&conf->keyboard);
break;
}
}
@ -91,12 +94,15 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
{ &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
{ &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
{ &ops, F71863FG_GPIO, PNP_IRQ0, },
{ &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
{ &ops, F71863FG_GPIO, },
{ &ops, F71863FG_VID, PNP_IO0, { 0x07f8, 0 }, },
{ &ops, F71863FG_SPI, },
{ &ops, F71863FG_PME, },
};

13
src/superio/fintek/f71889/superio.c
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@ -40,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev)
static void f71889_init(device_t dev)
{
struct superio_fintek_f71889_config *conf = dev->chip_info;
struct resource *res0, *res1;
struct resource *res0;
if (!dev->enabled)
return;
@ -57,7 +57,6 @@ static void f71889_init(device_t dev)
break;
case F71889_KBC:
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
pc_keyboard_init(&conf->keyboard);
break;
}
@ -95,14 +94,14 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
{ &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
{ &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
{ &ops, F71889_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, },
{ &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
{ &ops, F71889_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, },
{ &ops, F71889_GPIO, },
{ &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, },
{ &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, },
{ &ops, F71889_SPI, },
{ &ops, F71889_PME, },
{ &ops, F71889_VREF, },

2
src/superio/intel/i3100/Makefile.inc
View File

@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c

21
src/superio/intel/i3100/i3100.h
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@ -18,11 +18,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Datasheet: http://www.intel.com/design/intarch/datashts/313458.htm */
/*
* Datasheet:
* - Name: Intel 3100 Chipset
* - URL: http://www.intel.com/design/intarch/datashts/313458.htm
* - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf
* - Revision / Date: 007, October 2008
* - Order number: 313458-007US
*/
#ifndef SUPERIO_INTEL_I3100_I3100_H
#define SUPERIO_INTEL_I3100_I3100_H
/*
* The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is
* very similar to a Super I/O, both in functionality and config mechanism.
*
* The SIW contains:
* - UART(s)
* - Serial interrupt controller
* - Watchdog timer (WDT)
* - LPC interface
*/
/* Logical device numbers (LDNs). */
#define I3100_SP1 0x04 /* Com1 */
#define I3100_SP2 0x05 /* Com2 */
#define I3100_WDT 0x06 /* Watchdog timer */

13
src/superio/intel/i3100/i3100_early_serial.c
View File

@ -21,8 +21,7 @@
#include <arch/romcc_io.h>
#include "i3100.h"
static void i3100_sio_write(u8 port, u8 ldn, u8 index,
u8 value)
static void i3100_sio_write(u8 port, u8 ldn, u8 index, u8 value)
{
outb(0x07, port);
outb(ldn, port + 1);
@ -32,21 +31,21 @@ static void i3100_sio_write(u8 port, u8 ldn, u8 index,
static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
{
/* Enter configuration state */
/* Enter configuration state. */
outb(0x80, port);
outb(0x86, port);
/* Enable serial port */
/* Enable serial port. */
i3100_sio_write(port, ldn, 0x30, 0x01);
/* Set serial port IO region */
/* Set serial port I/O region. */
i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
/* Enable device interrupts, set UART_CLK predivide to 26 */
/* Enable device interrupts, set UART_CLK predivide to 26. */
i3100_sio_write(port, 0x00, 0x29, 0x0b);
/* Exit configuration state */
/* Exit configuration state. */
outb(0x68, port);
outb(0x08, port);
}

3
src/superio/intel/i3100/superio.c
View File

@ -43,9 +43,8 @@ static void i3100_init(device_t dev)
struct superio_intel_i3100_config *conf;
struct resource *res0;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;