amd/gardenia: Fix most checkpatch errors
Correct all checkpatch errors but leave two errors in place that are caused by AMD typing. Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
Martin Roth
parent
2df118cdf0
commit
7d4ba55343
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@ -28,10 +28,10 @@
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#include <dimmSpd.h>
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#include <agesawrapper.h>
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static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
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static AGESA_STATUS Fch_Oem_config(UINT32 Func,
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UINT32 FchData, VOID *ConfigPtr);
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const BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
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{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
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{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
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{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
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@ -83,7 +83,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
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if (StdHeader->Func == AMD_INIT_RESET) {
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FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
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FCH_RESET_DATA_BLOCK *FchParams_reset =
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(FCH_RESET_DATA_BLOCK *)FchData;
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printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
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FchParams_reset->FchReset.SataEnable = hudson_sata_enable();
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FchParams_reset->FchReset.IdeEnable = hudson_ide_enable();
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@ -102,7 +103,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
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FchParams_env->Usb.Xhci0Enable = FALSE;
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#endif
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FchParams_env->Usb.Xhci1Enable = FALSE;
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FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
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/* 8: If USB3 port is unremoveable. */
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FchParams_env->Usb.USB30PortInit = 8;
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/* SATA configuration */
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FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
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@ -17,12 +17,13 @@
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#include <PlatformMemoryConfiguration.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* Initialize Port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
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static const PCIe_PORT_DESCRIPTOR PortList[] = {
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/* Init port descriptor (PCIe port, Lanes 7:4, D2F1) for x4 slot */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
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PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 4, 7),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
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2, 1,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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@ -31,8 +32,9 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* Initialize Port descriptor (PCIe port, Lanes 1:0, D2F2) for M.2 */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 0, 1),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 2,
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PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
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2, 2,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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@ -40,8 +42,9 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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},
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 3,
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PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 1, 1),
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PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db,
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2, 3,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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@ -50,8 +53,9 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* Initialize Port descriptor (PCIe port, Lane 2, D2F4) for x1 slot */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
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2, 4,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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@ -60,8 +64,9 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* Initialize Port descriptor (PCIe port, Lane3, D2F5) for SD */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
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PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
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PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
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2, 5,
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HotplugDisabled,
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PcieGenMaxSupported,
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PcieGenMaxSupported,
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@ -70,24 +75,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* Initialize Port descriptor (PCIe port, Lane 1, D2F3) for M.2 */
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};
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static const PCIe_DDI_DESCRIPTOR DdiList [] = {
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static const PCIe_DDI_DESCRIPTOR DdiList[] = {
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/* DDI0 - eDP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux1, Hdp1)
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},
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/* DDI1 - DP */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
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},
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/* DDI2 - HDMI */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
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PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
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PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
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},
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};
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@ -98,8 +103,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
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.DdiLinkList = DdiList
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};
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static const UINT32 AzaliaCodecAlc286Table[] =
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{
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static const UINT32 AzaliaCodecAlc286Table[] = {
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0x00172051, 0x001721C7, 0x00172222, 0x00172310,
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0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00,
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0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7,
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@ -120,19 +124,18 @@ static const UINT32 AzaliaCodecAlc286Table[] =
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0xffffffff
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};
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CONST CODEC_VERB_TABLE_LIST CodecTableList[] =
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{
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CONST CODEC_VERB_TABLE_LIST CodecTableList[] = {
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{ (UINT32) 0x10ec0286, AzaliaCodecAlc286Table},
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{ (UINT32) 0x0FFFFFFFF, (UINT32 *)0x0FFFFFFFF}
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};
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/*---------------------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This is the stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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* This is the stub function will call the host environment through the
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* binary block interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] **PeiServices
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@ -141,28 +144,30 @@ CONST CODEC_VERB_TABLE_LIST CodecTableList[] =
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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VOID OemCustomizeInitEarly (
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IN OUT AMD_EARLY_PARAMS *InitEarly
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)
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/*---------------------------------------------------------------------------*/
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VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
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{
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InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
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InitEarly->PlatformConfig.AzaliaCodecVerbTable = (UINT64)(UINTN)CodecTableList;
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InitEarly->PlatformConfig.AzaliaCodecVerbTable =
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(UINT64)(UINTN)CodecTableList;
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}
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static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
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DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
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NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
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MOTHER_BOARD_LAYERS (LAYERS_6),
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MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
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NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
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MOTHER_BOARD_LAYERS(LAYERS_6),
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MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
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CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
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0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
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PSO_END
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};
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void OemPostParams(AMD_POST_PARAMS *PostParams)
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{
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PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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PostParams->MemConfig.PlatformMemoryConfiguration =
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(PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
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}
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@ -34,24 +34,25 @@ unsigned long acpi_fill_madt(unsigned long current)
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current = acpi_create_madt_lapics(current);
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/* Write Kern IOAPIC, only one */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
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IO_APIC_ADDR, 0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
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/* TODO: Remove the hardcode */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
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IO_APIC2_ADDR, 24);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
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CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, 0xF);
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current += acpi_create_madt_irqoverride(
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(acpi_madt_irqoverride_t *)current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride(
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(acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xF);
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/* 0: mean bus 0--->ISA */
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/* 0: PIC 0 */
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/* 2: APIC 2 */
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/* 5 mean: 0101 --> Edge-triggered, Active high */
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/* create all subtables for processors */
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
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current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
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0xff, 5, 1);
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/* 1: LINT1 connect to NMI */
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return current;
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@ -23,7 +23,7 @@ DefinitionBlock (
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
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/* #include <arch/x86/acpi/debug.asl> */ /* as needed */
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/* Globals for the platform */
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#include "acpi/mainboard.asl"
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@ -48,7 +48,7 @@ DefinitionBlock (
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
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/* IRQ Routing mapping for this platform (in \_SB scope) */
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#include "acpi/routing.asl"
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Device(PWRB) {
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@ -15,7 +15,7 @@
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#include "fchec.h"
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void agesawrapper_fchecfancontrolservice()
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void agesawrapper_fchecfancontrolservice(void)
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{
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FCH_DATA_BLOCK LateParams;
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@ -26,36 +26,38 @@ void agesawrapper_fchecfancontrolservice()
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
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/* SMBUS Address for SMBUS based temperature sensor */
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */
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/* PWM steping rate in unit of PWM level percentage */
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01;
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LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
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/* IMC Fan Policy temperature thresholds */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 in oC */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 in oC */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 undefined */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 undefined */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 undefined */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 undefined */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 undefined */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*crit threshold */
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LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
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/* IMC Fan Policy PWM Settings */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percent */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percent */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percent */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percent */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percent */
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LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percent */
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||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percent */
|
||||
LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percent */
|
||||
|
||||
LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;
|
||||
|
||||
|
|
|
|||
|
|
@ -92,9 +92,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
if (sum != pirq->checksum)
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
|
||||
|
||||
|
|
|
|||
|
|
@ -31,41 +31,41 @@
|
|||
* MP Tables. TODO: Make ACPI use these values too.
|
||||
*/
|
||||
const u8 mainboard_picr_data[] = {
|
||||
[0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
|
||||
[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
|
||||
[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
|
||||
[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
|
||||
[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F,
|
||||
[0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
|
||||
[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
|
||||
[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
|
||||
[0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
};
|
||||
|
||||
const u8 mainboard_intr_data[] = {
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
|
||||
[0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
|
||||
[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
|
||||
[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
|
||||
[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
|
||||
[0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
|
||||
[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
|
||||
[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
|
||||
[0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
|
||||
[0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
|
||||
[0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
[0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
|
||||
[0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/* PIRQ Setup */
|
||||
|
|
@ -82,7 +82,8 @@ static void pirq_setup(void)
|
|||
*************************************************/
|
||||
static void gardenia_enable(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
printk(BIOS_INFO, "Mainboard "
|
||||
CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
|
||||
|
||||
/* Initialize the PIRQ data structures for consumption */
|
||||
pirq_setup();
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include <soc/hudson.h>
|
||||
#include <amd_pci_util.h>
|
||||
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
|
||||
static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
|
||||
{
|
||||
mc->mpc_length += length;
|
||||
mc->mpc_entry_count++;
|
||||
|
|
@ -75,16 +75,20 @@ static void *smp_write_config_table(void *v)
|
|||
|
||||
smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
smp_write_lintsrc(mc, (type), \
|
||||
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \
|
||||
(intr), (apicid), (pin))
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, int_sign, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
smp_write_intsrc(mc, mp_INT, \
|
||||
MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \
|
||||
(((dev)<<2)|(int_sign)), ioapic_id, (pin))
|
||||
|
||||
/* Internal VGA */
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
|
||||
|
|
@ -146,7 +150,7 @@ static void *smp_write_config_table(void *v)
|
|||
/* FCH PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
|
|
|||
|
|
@ -44,7 +44,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|||
|
||||
/* Halt if there was a built in self test failure */
|
||||
post_code(0x34);
|
||||
report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
|
||||
/* Mask bit 31. One result of Silicon Observation */
|
||||
report_bist_failure(bist & 0x7FFFFFFF);
|
||||
|
||||
/* Load MPB */
|
||||
val = cpuid_eax(1);
|
||||
|
|
|
|||
Loading…
Reference in New Issue