tigerlake: enable DPTF functionality for volteer

Enable DPTF functionality for volteer platform

BRANCH=None
BUG=b:149722146
TEST=Built and tested on volteer system

Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/volteer/dsdt.asl

@@ -52,6 +52,17 @@ DefinitionBlock(
 		#include <ec/google/chromeec/acpi/ec.asl>
 	}
 
+	/* Dynamic Platform Thermal Framework */
+	Scope (\_SB)
+	{
+		/* Per board variant specific definitions. */
+		#include <variant/acpi/dptf.asl>
+		/* Include soc specific DPTF changes */
+		#include <soc/intel/common/acpi/dptf.asl>
+		/* Include common dptf ASL files */
+		#include <soc/intel/common/acpi/dptf/dptf.asl>
+	}
+
 	#include <southbridge/intel/common/acpi/sleepstates.asl>
 
 #if CONFIG(VARIANT_HAS_MIPI_CAMERA)

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -170,6 +170,16 @@ chip soc/intel/tigerlake
 	# Enable S0ix
 	register "s0ix_enable" = "1"
 
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 60,
+	}"
+
+	register "Device4Enable" = "1"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/volteer/variants/baseboard/include/baseboard/acpi/dptf.asl

@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#define DPTF_CPU_PASSIVE       95
+#define DPTF_CPU_CRITICAL      105
+#define DPTF_CPU_ACTIVE_AC0    85
+#define DPTF_CPU_ACTIVE_AC1    80
+#define DPTF_CPU_ACTIVE_AC2    75
+#define DPTF_CPU_ACTIVE_AC3    70
+#define DPTF_CPU_ACTIVE_AC4    65
+
+#define DPTF_TSR0_SENSOR_ID    0
+#define DPTF_TSR0_SENSOR_NAME  "Thermal Sensor 1"
+#define DPTF_TSR0_PASSIVE      65
+#define DPTF_TSR0_CRITICAL     75
+#define DPTF_TSR0_ACTIVE_AC0   50
+#define DPTF_TSR0_ACTIVE_AC1   47
+#define DPTF_TSR0_ACTIVE_AC2   45
+#define DPTF_TSR0_ACTIVE_AC3   42
+#define DPTF_TSR0_ACTIVE_AC4   39
+
+#define DPTF_TSR1_SENSOR_ID    1
+#define DPTF_TSR1_SENSOR_NAME  "Thermal Sensor 2"
+#define DPTF_TSR1_PASSIVE      65
+#define DPTF_TSR1_CRITICAL     75
+#define DPTF_TSR1_ACTIVE_AC0   50
+#define DPTF_TSR1_ACTIVE_AC1   47
+#define DPTF_TSR1_ACTIVE_AC2   45
+#define DPTF_TSR1_ACTIVE_AC3   42
+#define DPTF_TSR1_ACTIVE_AC4   39
+
+#define DPTF_TSR2_SENSOR_ID    1
+#define DPTF_TSR2_SENSOR_NAME  "Thermal Sensor 3"
+#define DPTF_TSR2_PASSIVE      65
+#define DPTF_TSR2_CRITICAL     75
+#define DPTF_TSR2_ACTIVE_AC0   50
+#define DPTF_TSR2_ACTIVE_AC1   47
+#define DPTF_TSR2_ACTIVE_AC2   45
+#define DPTF_TSR2_ACTIVE_AC3   42
+#define DPTF_TSR2_ACTIVE_AC4   39
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+       Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+       Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 },  /* 1.5A */
+       Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 },  /* 1.0A */
+       Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },   /* 0.5A */
+})
+
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+       0,      // Revision
+       /*
+        * TODO : Need to update this Table after characterization.
+        *        These are initial reference values.
+        */
+       /* Control, Trip Point, Speed, NoiseLevel, Power */
+       Package () {90,         0xFFFFFFFF,     6700,   220,    2200},
+       Package () {80,         0xFFFFFFFF,     5800,   180,    1800},
+       Package () {70,         0xFFFFFFFF,     5000,   145,    1450},
+       Package () {60,         0xFFFFFFFF,     4900,   115,    1150},
+       Package () {50,         0xFFFFFFFF,     3838,   90,     900},
+       Package () {40,         0xFFFFFFFF,     2904,   55,     550},
+       Package () {30,         0xFFFFFFFF,     2337,   30,     300},
+       Package () {20,         0xFFFFFFFF,     1608,   15,     150},
+       Package () {10,         0xFFFFFFFF,     800,    10,     100},
+       Package () {0,          0xFFFFFFFF,     0,      0,      50}
+})
+
+Name (DART, Package () {
+       /* Fan effect on CPU */
+       0,      // Revision
+       Package () {
+               /*
+                * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+                *      AC7, AC8, AC9
+                */
+               \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 69, 56, 46, 36, 0, 0,
+                       0, 0, 0
+       },
+       Package () {
+               \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 0, 0,
+                       0, 0, 0
+       },
+       Package () {
+               \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
+                       0, 0, 0
+       },
+       Package () {
+               \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0,
+                       0, 0, 0
+       }
+})
+
+
+Name (DTRT, Package () {
+       /* CPU Throttle Effect on CPU */
+       Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+       /* CPU Throttle Effect on TSR0 sensor */
+       Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 },
+
+       /* Charger Throttle Effect on Charger (TSR1) */
+       Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
+
+       /* CPU Throttle Effect on TSR2 sensor */
+       Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+       0x2,            /* Revision */
+       Package () {    /* Power Limit 1 */
+               0,      /* PowerLimitIndex, 0 for Power Limit 1 */
+               3000,   /* PowerLimitMinimum */
+               15000,  /* PowerLimitMaximum */
+               28000,  /* TimeWindowMinimum */
+               32000,  /* TimeWindowMaximum */
+               200     /* StepSize */
+       },
+       Package () {    /* Power Limit 2 */
+               1,      /* PowerLimitIndex, 1 for Power Limit 2 */
+               15000,  /* PowerLimitMinimum */
+               60000,  /* PowerLimitMaximum */
+               28000,  /* TimeWindowMinimum */
+               32000,  /* TimeWindowMaximum */
+               1000    /* StepSize */
+       }
+})

src/mainboard/google/volteer/variants/halvor/include/variant/acpi/dptf.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/dptf.asl>

src/mainboard/google/volteer/variants/malefor/include/variant/acpi/dptf.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/dptf.asl>

src/mainboard/google/volteer/variants/ripto/include/variant/acpi/dptf.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/dptf.asl>

src/mainboard/google/volteer/variants/trondo/include/variant/acpi/dptf.asl

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/acpi/dptf.asl>

src/soc/intel/common/acpi/dptf.asl

@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define DPTF_CPU_DEVICE		TCPU
+#define DPTF_CPU_ADDR		0x00040000
+
+#ifndef DPTF_CPU_PASSIVE
+#define DPTF_CPU_PASSIVE	80
+#endif
+
+#ifndef DPTF_CPU_CRITICAL
+#define DPTF_CPU_CRITICAL	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC0
+#define DPTF_CPU_ACTIVE_AC0	90
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC1
+#define DPTF_CPU_ACTIVE_AC1	80
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC2
+#define DPTF_CPU_ACTIVE_AC2	70
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC3
+#define DPTF_CPU_ACTIVE_AC3	60
+#endif
+
+#ifndef DPTF_CPU_ACTIVE_AC4
+#define DPTF_CPU_ACTIVE_AC4	50
+#endif

src/soc/intel/tigerlake/fsp_params.c

@@ -193,6 +193,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
 	params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 
+	/* Enable TCPU for processor thermal control */
+	params->Device4Enable = config->Device4Enable;
+
 	/* LAN */
 	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
 	if (!dev)