soc/intel/baytrail: Don't reinitialize SPI after lockdown

With the common southbridge SPI code reinitialization after lockdown
is not necessary, hence the SMM finalize call becomes a no-op.

Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36008
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-10-13 23:29:41 +02:00 committed by Patrick Georgi
parent b48d63359b
commit 7d802a48f3
2 changed files with 0 additions and 23 deletions

View File

@ -229,22 +229,6 @@ static void southbridge_smi_gsmi(void)
*ret = gsmi_exec(sub_command, param);
}
static void finalize(void)
{
static int finalize_done;
if (finalize_done) {
printk(BIOS_DEBUG, "SMM already finalized.\n");
return;
}
finalize_done = 1;
#if CONFIG(SPI_FLASH_SMM)
/* Re-init SPI driver to handle locked BAR */
spi_init();
#endif
}
/*
* soc_legacy: A payload (Depthcharge) has indicated that the
* legacy payload (SeaBIOS) is being loaded. Switch devices that are
@ -348,10 +332,6 @@ static void southbridge_smi_apmc(void)
if (CONFIG(ELOG_GSMI))
southbridge_smi_gsmi();
break;
case APM_CNT_FINALIZE:
finalize();
break;
case APM_CNT_LEGACY:
soc_legacy();
break;

View File

@ -577,9 +577,6 @@ static void finalize_chipset(void *unused)
write32(spi + UVSCC, cfg.uvscc);
write32(spi + LVSCC, cfg.lvscc | VCL);
}
printk(BIOS_DEBUG, "Finalizing SMM.\n");
outb(APM_CNT_FINALIZE, APM_CNT);
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);