soc/intel/baytrail: Don't reinitialize SPI after lockdown
With the common southbridge SPI code reinitialization after lockdown is not necessary, hence the SMM finalize call becomes a no-op. Change-Id: Ie73a0adc120731d541a772e09f3482902771b9eb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36008 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -229,22 +229,6 @@ static void southbridge_smi_gsmi(void)
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*ret = gsmi_exec(sub_command, param);
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*ret = gsmi_exec(sub_command, param);
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}
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}
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static void finalize(void)
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{
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static int finalize_done;
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if (finalize_done) {
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printk(BIOS_DEBUG, "SMM already finalized.\n");
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return;
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}
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finalize_done = 1;
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#if CONFIG(SPI_FLASH_SMM)
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/* Re-init SPI driver to handle locked BAR */
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spi_init();
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#endif
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}
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/*
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/*
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* soc_legacy: A payload (Depthcharge) has indicated that the
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* soc_legacy: A payload (Depthcharge) has indicated that the
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* legacy payload (SeaBIOS) is being loaded. Switch devices that are
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* legacy payload (SeaBIOS) is being loaded. Switch devices that are
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@ -348,10 +332,6 @@ static void southbridge_smi_apmc(void)
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if (CONFIG(ELOG_GSMI))
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if (CONFIG(ELOG_GSMI))
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southbridge_smi_gsmi();
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southbridge_smi_gsmi();
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break;
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break;
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case APM_CNT_FINALIZE:
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finalize();
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break;
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case APM_CNT_LEGACY:
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case APM_CNT_LEGACY:
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soc_legacy();
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soc_legacy();
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break;
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break;
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@ -577,9 +577,6 @@ static void finalize_chipset(void *unused)
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write32(spi + UVSCC, cfg.uvscc);
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write32(spi + UVSCC, cfg.uvscc);
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write32(spi + LVSCC, cfg.lvscc | VCL);
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write32(spi + LVSCC, cfg.lvscc | VCL);
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}
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}
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printk(BIOS_DEBUG, "Finalizing SMM.\n");
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outb(APM_CNT_FINALIZE, APM_CNT);
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}
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}
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
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BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL);
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