smsc/sch5147: Implement ACPI handling of a few LDN
Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
a1e46aea79
commit
7d81718cb8
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/* TODO */
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#undef SUPERIO_DEV
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#undef SUPERIO_PNP_BASE
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#undef SCH5147_SHOW_UARTA
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#undef SCH5147_SHOW_UARTB
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#undef SCH5147_SHOW_KBC
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#undef SCH5147_SHOW_HWMON
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define SCH5147_SHOW_UARTA
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#define SCH5147_SHOW_UARTB
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#define SCH5147_SHOW_KBC
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#include <superio/smsc/sch5147/acpi/superio.asl>
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the SCH5147 SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices and controlling power
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* saving mode on logical devices or the whole chip.
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*
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* LDN State
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* 0x0 FDC Not implemented
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* 0x3 PP Not implemented
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* 0x4 UARTA Implemented
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* 0x5 UARTB Implemented
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* 0x7 KBC Implemented
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* 0xa Runtime reg Not implemented
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/o address of the first PnP configuration register
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* SCH5147_SHOW_UARTA If defined, UARTA will be exposed.
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* SCH5147_SHOW_UARTB If defined, UARTB will be exposed.
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* SCH5147_SHOW_KBC If defined, the KBC will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME SCH5147
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("SMSC SCH5147 Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* Mutex for accesses to the configuration ports */
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Mutex(CRMX, 1)
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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Offset (0x72),
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PNP_IRQ1, 8, /* Second IRQ */
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Offset (0x74),
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PNP_DMA0, 8, /* DMA */
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}
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Method (_CRS)
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{
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/* Announce the used i/o ports to the OS */
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Return (ResourceTemplate () {
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FixedIO (SUPERIO_PNP_BASE, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x55
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#define PNP_EXIT_MAGIC_1ST 0xaa
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#include <superio/acpi/pnp_config.asl>
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#ifdef SCH5147_SHOW_UARTA
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 4
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SCH5147_SHOW_UARTB
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 5
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef SCH5147_SHOW_KBC
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/* we can't read back the IO resources so hardcode them */
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#define SUPERIO_KBC_LDN 7
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Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
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Name (_HID, EisaId ("PNP0303"))
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Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN))
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Method (_STA)
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{
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PNP_GENERIC_STA(SUPERIO_KBC_LDN)
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}
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Method (_DIS)
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{
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ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
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Store (Zero, PNP_DEVICE_ACTIVE)
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EXIT_CONFIG_MODE ()
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#if defined(SUPERIO_KBC_PS2LDN)
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Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1)
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#elif defined(SUPERIO_KBC_PS2M)
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Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
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#endif
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}
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Method (_PSC) {
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PNP_DEFAULT_PSC
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}
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Method (_CRS, 0, Serialized)
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{
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Name (CRS, ResourceTemplate () {
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FixedIO (0x0060, 0x01)
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FixedIO (0x0064, 0x01)
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IRQNoFlags (IR0) {}
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})
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ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
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PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
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EXIT_CONFIG_MODE ()
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Return (CRS)
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}
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Name (_PRS, ResourceTemplate ()
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{
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StartDependentFn (0,0) {
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FixedIO (0x0060, 0x01)
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FixedIO (0x0064, 0x01)
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IRQNoFlags () {1}
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}
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EndDependentFn()
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})
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Method (_SRS, 1, Serialized)
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{
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Name (TMPL, ResourceTemplate () {
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FixedIO (0x0060, 0x01)
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FixedIO (0x0064, 0x01)
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IRQNoFlags (IR0) {}
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})
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ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
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PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
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Store (One, PNP_DEVICE_ACTIVE)
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EXIT_CONFIG_MODE ()
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Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
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}
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}
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Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) {
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Name (_HID, EisaId ("PNP0F13"))
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Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN))
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Method (_STA)
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{
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Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ())
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}
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Method (_PSC) {
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Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ())
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}
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Method (_CRS, 0, Serialized)
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{
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Name (CRS, ResourceTemplate () {
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IRQNoFlags (IR1) {}
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})
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ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
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PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
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EXIT_CONFIG_MODE ()
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Return (CRS)
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}
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Name (_PRS, ResourceTemplate ()
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{
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StartDependentFn (0,0) {
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IRQNoFlags () {12}
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}
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EndDependentFn()
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})
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Method (_SRS, 1, Serialized)
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{
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Name (TMPL, ResourceTemplate () {
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IRQNoFlags (IR1) {}
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})
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ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
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PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
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EXIT_CONFIG_MODE ()
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}
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}
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#endif
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}
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