mb/google/brya: Update ddr config

Fixed ddr config to override the FSP default value.

BUG=b:182772421
TEST=Built image and passed memory training.

Without this change:
RcompTarget on Lpddr4x = { 40, 40, 30, 30, 30 }

With this change:
RcompTarget on Lpddr4x = { 40, 30, 30, 30, 30 }

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib07ff36496828b5de78ed928b294a400ad08865f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/brya/variants/baseboard/memory.c

@@ -7,6 +7,14 @@
 static const struct mb_cfg baseboard_memcfg = {
 	.type = MEM_TYPE_LP4X,
 
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {40, 30, 30, 30, 30},
+	},
+
 	/* DQ byte map */
 	.lpx_dq_map = {
 		.ddr0 = {