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mb/google/brya: Update memory DQ map 

Follow latest schematic to update the DQ map.

BUG=b:218939997
TEST=boot into OS without issue.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eric Lai 2022-02-11 14:53:39 +08:00 committed by Felix Held
parent 5e8dd5d24a
commit 7d8b553608
1 changed files with 20 additions and 20 deletions
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40
src/mainboard/google/brya/variants/baseboard/brya/memory.c
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@ -18,48 +18,48 @@ static const struct mb_cfg baseboard_memcfg = {
/* DQ byte map */ /* DQ byte map */
.lpx_dq_map = { .lpx_dq_map = {
.ddr0 = { .ddr0 = {
.dq0 = { 0, 1, 2, 3, 4, 5, 6, 7, }, .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, },
.dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, },
}, },
.ddr1 = { .ddr1 = {
.dq0 = { 7, 2, 6, 3, 5, 1, 4, 0, }, .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, },
.dq1 = { 10, 8, 9, 11, 15, 12, 14, 13, }, .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, },
}, },
.ddr2 = { .ddr2 = {
.dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, },
.dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, },
}, },
.ddr3 = { .ddr3 = {
.dq0 = { 7, 0, 1, 6, 5, 4, 2, 3, }, .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, },
.dq1 = { 15, 14, 8, 9, 10, 12, 11, 13, }, .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, },
}, },
.ddr4 = { .ddr4 = {
.dq0 = { 3, 2, 1, 0, 4, 5, 6, 7, }, .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, },
.dq1 = { 12, 13, 14, 15, 11, 10, 9, 8, }, .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, },
}, },
.ddr5 = { .ddr5 = {
.dq0 = { 3, 4, 2, 5, 0, 6, 1, 7, }, .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, },
.dq1 = { 13, 12, 11, 10, 14, 15, 9, 8, }, .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, },
}, },
.ddr6 = { .ddr6 = {
.dq0 = { 3, 2, 1, 0, 7, 4, 5, 6, }, .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, },
.dq1 = { 15, 14, 13, 12, 8, 9, 10, 11, }, .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, },
}, },
.ddr7 = { .ddr7 = {
.dq0 = { 3, 4, 2, 5, 1, 0, 7, 6, }, .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, },
.dq1 = { 15, 14, 9, 8, 12, 10, 11, 13, }, .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, },
}, },
}, },
/* DQS CPU<>DRAM map */ /* DQS CPU<>DRAM map */
.lpx_dqs_map = { .lpx_dqs_map = {
.ddr0 = { .dqs0 = 0, .dqs1 = 1 }, .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 }, .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 }, .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 }, .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 0, .dqs1 = 1 }, .ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 }, .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 }, .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }, .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
}, },