This patch fixes the superio of the khepri 2100e as detected:
> superiotool r2922 > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x0d) at 0x2e Don't use the non-working trident driver for the blade3d (onboard vga in the rom emulator has not been tested either) It also adds some preliminary CAR support to the board, so it has a chance to build again. This board was broken since a couple of months, and the changes are minimal, so I consider this a trivial change -- It doesn't change anything that was used, obviously Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
9c84a46007
commit
7d8cd7602f
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@ -47,8 +47,27 @@ if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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dir /drivers/trident/blade3d
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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makerule ./auto.o
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
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end
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else
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makerule ./auto.inc
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depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
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action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
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action "perl -e 's/.rodata/.rom.data/g' -pi $@"
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action "perl -e 's/.text/.section .rom.text/g' -pi $@"
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end
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end
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else
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##
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## Romcc output
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##
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@ -71,13 +90,27 @@ makerule ./auto.inc
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action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/entry16.inc
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ldscript /cpu/x86/16bit/entry16.lds
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end
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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ldscript /cpu/x86/32bit/entry32.lds
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end
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if CONFIG_USE_INIT
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ldscript /cpu/amd/car/cache_as_ram.lds
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end
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end
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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@ -91,23 +124,36 @@ else
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end
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### Should this be in the northbridge code?
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if USE_DCACHE_RAM
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else
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mainboardinit arch/i386/lib/cpu_reset.inc
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end
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if USE_DCACHE_RAM
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##
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## Setup Cache-As-Ram
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##
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mainboardinit cpu/amd/car/cache_as_ram.inc
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end
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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if USE_DCACHE_RAM
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ldscript /arch/i386/lib/failover.lds
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else
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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end
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###
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### O.k. We aren't just an intermediary anymore!
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@ -116,6 +162,20 @@ end
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##
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## Setup RAM
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##
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if USE_DCACHE_RAM
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if CONFIG_USE_INIT
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initobject auto.o
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else
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mainboardinit ./auto.inc
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end
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else
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu/enable_fpu.inc
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mainboardinit cpu/x86/mmx/enable_mmx.inc
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mainboardinit cpu/x86/sse/enable_sse.inc
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@ -123,13 +183,22 @@ mainboardinit ./auto.inc
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mainboardinit cpu/x86/sse/disable_sse.inc
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mainboardinit cpu/x86/mmx/disable_mmx.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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end
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config chip.h
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# FIXME: ROM for onboard VGA
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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chip cpu/amd/socket_940
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device apic 1 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8
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device pci 18.0 on end # LDT 0
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@ -148,36 +217,45 @@ chip northbridge/amd/amdk8/root_complex
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device pci 1.0 on end
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end
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device pci 1.0 on
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chip superio/nsc/pc87360
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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chip superio/winbond/w83627hf
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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device pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.2 off # Com 2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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device pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # Com 1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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device pnp 2e.3 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.4 off end # SWC
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device pnp 2e.5 off end # Mouse
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.7 off end # GPIO
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device pnp 2e.8 off end # ACB
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device pnp 2e.9 off end # FSCM
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device pnp 2e.a off end # WDT
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device pnp 2e.6 off # CIR
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io 0x60 = 0x100
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end
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device pnp 2e.7 off # GAME_MIDI_GIPO1
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io 0x60 = 0x220
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io 0x62 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.8 off end # GPIO2
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device pnp 2e.9 off end # GPIO3
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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irq 0x70 = 5
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end
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end
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end
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device pci 1.1 on end
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@ -201,13 +279,5 @@ chip northbridge/amd/amdk8/root_complex
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device pci 19.3 on end
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end
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end
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device apic_cluster 0 on
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chip cpu/amd/socket_940
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device apic 0 on end
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end
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chip cpu/amd/socket_940
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device apic 1 on end
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end
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end
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end
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@ -7,6 +7,7 @@ uses IRQ_SLOT_COUNT
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uses HAVE_OPTION_TABLE
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uses CONFIG_MAX_CPUS
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uses CONFIG_MAX_PHYSICAL_CPUS
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uses CONFIG_LOGICAL_CPUS
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uses CONFIG_IOAPIC
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uses CONFIG_SMP
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uses FALLBACK_SIZE
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@ -18,6 +19,7 @@ uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_ROM_PAYLOAD_START
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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@ -31,6 +33,8 @@ uses LB_CKS_LOC
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uses MAINBOARD_PART_NUMBER
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uses MAINBOARD_VENDOR
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uses MAINBOARD
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uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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uses LINUXBIOS_EXTRA_VERSION
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uses _RAMBASE
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uses TTYS0_BAUD
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@ -40,11 +44,20 @@ uses DEFAULT_CONSOLE_LOGLEVEL
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uses MAXIMUM_CONSOLE_LOGLEVEL
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uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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uses CONFIG_CONSOLE_SERIAL8250
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uses HAVE_INIT_TIMER
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uses CONFIG_GDB_STUB
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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uses CONFIG_CHIP_NAME
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses HW_MEM_HOLE_SIZEK
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uses USE_DCACHE_RAM
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uses DCACHE_RAM_BASE
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uses DCACHE_RAM_SIZE
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uses CONFIG_USE_INIT
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###
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@ -59,6 +72,8 @@ default ROM_SIZE=524288
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##
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## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
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##
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#default FALLBACK_SIZE=131072
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#256K
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default FALLBACK_SIZE=0x40000
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##
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@ -75,7 +90,7 @@ default HAVE_HARD_RESET=1
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## Build code to export a programmable irq routing table
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##
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default HAVE_PIRQ_TABLE=1
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default IRQ_SLOT_COUNT=9
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default IRQ_SLOT_COUNT=15
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##
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## Build code to export an x86 MP table
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@ -100,8 +115,28 @@ default LB_CKS_LOC=123
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## Only worry about 2 micro processors
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##
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default CONFIG_SMP=1
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default CONFIG_MAX_CPUS=2
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default CONFIG_MAX_CPUS=4
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default CONFIG_MAX_PHYSICAL_CPUS=2
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default CONFIG_LOGICAL_CPUS=1
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#CHIP_NAME ?
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default CONFIG_CHIP_NAME=1
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#1G memory hole
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default HW_MEM_HOLE_SIZEK=0x100000
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#VGA Console
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default CONFIG_CONSOLE_VGA=1
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default CONFIG_PCI_ROM_RUN=1
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##
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## enable CACHE_AS_RAM specifics
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##
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default USE_DCACHE_RAM=1
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default DCACHE_RAM_BASE=0xcf000
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default DCACHE_RAM_SIZE=0x1000
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default CONFIG_USE_INIT=0
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##
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## Build code to setup a generic IOAPIC
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@ -113,6 +148,8 @@ default CONFIG_IOAPIC=1
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##
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default MAINBOARD_PART_NUMBER="Khepri"
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default MAINBOARD_VENDOR="Newisys"
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default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x17c2
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default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x0010
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###
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### LinuxBIOS layout values
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@ -156,6 +193,11 @@ default CONFIG_ROM_PAYLOAD = 1
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default CC="$(CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## Disable the gdb stub by default
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##
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default CONFIG_GDB_STUB=0
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##
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## The Serial Console
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##
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@ -19,11 +19,11 @@
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include <cpu/amd/model_fxx_rev.h>
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#include "superio/nsc/pc87360/pc87360_early_serial.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void hard_reset(void)
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{
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@ -115,7 +115,7 @@ static void main(unsigned long bist)
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k8_init_and_stop_secondaries();
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}
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/* Setup the console */
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pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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@ -0,0 +1,249 @@
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/*
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* This code is derived from the Tyan s2882 cache_as_ram_auto.c
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* Adapted by Stefan Reinauer <stepan@coresystems.de>
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* Additional (C) 2007 coresystems GmbH
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*/
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#define ASSEMBLY 1
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#define __ROMCC__
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/x86/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#if 0
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static void post_code(uint8_t value) {
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#if 1
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int i;
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for(i=0;i<0x80000;i++) {
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outb(value, 0x80);
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}
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#endif
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}
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#endif
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#if CONFIG_USE_INIT == 0
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#include "lib/memcpy.c"
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#endif
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#include "cpu/x86/lapic/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#include "cpu/amd/mtrr/amd_earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
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static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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||||
}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#define QRANK_DIMM_SUPPORT 1
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
/* newisys khepri does not want the default */
|
||||
#include "resourcemap.c"
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
#define SET_NB_CFG_54 1
|
||||
#endif
|
||||
#include "cpu/amd/dualcore/dualcore.c"
|
||||
|
||||
|
||||
#include "cpu/amd/car/copy_and_run.c"
|
||||
|
||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||
|
||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
|
||||
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
unsigned last_boot_normal_x = last_boot_normal();
|
||||
|
||||
/* Is this a cpu only reset? or Is this a secondary cpu? */
|
||||
if ((cpu_init_detectedx) || (!boot_cpu())) {
|
||||
if (last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the ck804 */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
// post_code(0x22);
|
||||
if (bios_reset_detected() && last_boot_normal_x) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
// post_code(0x23);
|
||||
__asm__ volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
|
||||
);
|
||||
|
||||
fallback_image:
|
||||
// post_code(0x25);
|
||||
;
|
||||
}
|
||||
#endif
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
|
||||
#if USE_FALLBACK_IMAGE == 1
|
||||
failover_process(bist, cpu_init_detectedx);
|
||||
#endif
|
||||
real_main(bist, cpu_init_detectedx);
|
||||
|
||||
}
|
||||
|
||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr [] = {
|
||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
unsigned bsp_apicid = 0;
|
||||
|
||||
struct mem_controller ctrl[8];
|
||||
unsigned nodes;
|
||||
|
||||
if (bist == 0) {
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx);
|
||||
}
|
||||
|
||||
// post_code(0x32);
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
setup_khepri_resource_map();
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 0));
|
||||
dump_pci_device(PCI_DEV(0, 0x19, 0));
|
||||
#endif
|
||||
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
|
||||
wait_all_core0_started();
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
// It is said that we should start core1 after all core0 launched
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
|
||||
needs_reset |= ht_setup_chains_x();
|
||||
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
nodes = get_nodes();
|
||||
//It's the time to set ctrl now;
|
||||
fill_mem_ctrl(nodes, ctrl, spd_addr);
|
||||
|
||||
enable_smbus();
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(nodes, ctrl);
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
post_cache_as_ram();
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue