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AGESA Hudson/Yangtze: Remove obsolete devicetree parameters 

Change-Id: Ic6affae7e508f28b131c7d07191289f4fcbf2d74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7599
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki 2014-11-21 08:40:43 +02:00
parent 96d92765e1
commit 7d8cde756e
7 changed files with 0 additions and 13 deletions
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1
src/mainboard/amd/parmer/devicetree.cb
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@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 off end # PCIe 1 device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2 device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3 device pci 15.3 off end # PCIe 3
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4" register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson end #chip southbridge/amd/hudson

1
src/mainboard/amd/thatcher/devicetree.cb
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@ -83,7 +83,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 off end # PCIe 1 device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2 device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3 device pci 15.3 off end # PCIe 3
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4" register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson end #chip southbridge/amd/hudson

1
src/mainboard/asus/f2a85-m/devicetree.cb
View File

@ -116,7 +116,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.2 off end # unused device pci 15.2 off end # unused
device pci 15.3 off end # unused device pci 15.3 off end # unused
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4" register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson end #chip southbridge/amd/hudson

2
src/mainboard/asus/f2a85-m_le/devicetree.cb
View File

@ -115,8 +115,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 on end # PCIe 1 onboard gigabit device pci 15.1 on end # PCIe 1 onboard gigabit
device pci 15.2 off end # unused device pci 15.2 off end # unused
device pci 15.3 off end # unused device pci 15.3 off end # unused
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4" register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson end #chip southbridge/amd/hudson

1
src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
View File

@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex
device pci 15.1 off end # PCIe 1 device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2 device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3 device pci 15.3 off end # PCIe 3
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4" register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson end #chip southbridge/amd/hudson

1
src/mainboard/lenovo/g505s/devicetree.cb
View File

@ -72,7 +72,6 @@ chip northbridge/amd/agesa/family15rl/root_complex
device pci 15.1 off end # PCIe 1 device pci 15.1 off end # PCIe 1
device pci 15.2 off end # PCIe 2 device pci 15.2 off end # PCIe 2
device pci 15.3 off end # PCIe 3 device pci 15.3 off end # PCIe 3
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "gpp_configuration" = "4" register "gpp_configuration" = "4"
end #chip southbridge/amd/hudson end #chip southbridge/amd/hudson

6
src/southbridge/amd/agesa/hudson/chip.h
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@ -22,14 +22,8 @@
struct southbridge_amd_agesa_hudson_config struct southbridge_amd_agesa_hudson_config
{ {
#if 1
u32 ide0_enable : 1;
u32 sata0_enable : 1;
u32 boot_switch_sata_ide : 1;
u32 hda_viddid;
u8 gpp_configuration; u8 gpp_configuration;
u8 sd_mode; u8 sd_mode;
#endif
}; };
#endif /* HUDSON_CHIP_H */ #endif /* HUDSON_CHIP_H */