AGESA binaryPI: Consolidate ACPI for IMC
Change-Id: Ieff6041f3c9ad02f9cebae0ec83d0898abb0d601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/18538 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
parent
24aea52e29
commit
7d9016931c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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//BTDC Due to IMC Fan, ACPI control codes
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCA,8
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}
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IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
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Offset(0x80),
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MSTI, 8,
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MITS, 8,
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MRG0, 8,
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MRG1, 8,
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MRG2, 8,
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MRG3, 8,
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}
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Method(WACK, 0)
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{
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Store(0, Local0)
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While (LNotEqual(Local0, 0xFA)) {
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Store(MRG0, Local0)
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Sleep(10)
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}
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}
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//Init
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Method (ITZE, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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@ -1,63 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCA,8
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}
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IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
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Offset(0x80),
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MSTI, 8,
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MITS, 8,
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MRG0, 8,
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MRG1, 8,
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MRG2, 8,
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MRG3, 8,
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}
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Method(WACK, 0)
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{
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Store(0, Local0)
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While (LNotEqual(Local0, 0xFA)) {
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Store(MRG0, Local0)
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Sleep(10)
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}
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}
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//Init
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Method (ITZE, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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@ -1,64 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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//BTDC Due to IMC Fan, ACPI control codes
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCA,8
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}
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IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
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Offset(0x80),
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MSTI, 8,
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MITS, 8,
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MRG0, 8,
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MRG1, 8,
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MRG2, 8,
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MRG3, 8,
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}
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Method(WACK, 0)
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{
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Store(0, Local0)
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While (LNotEqual(Local0, 0xFA)) {
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Store(MRG0, Local0)
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Sleep(10)
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}
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}
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//Init
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Method (ITZE, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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@ -1,63 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCA,8
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}
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IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
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Offset(0x80),
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MSTI, 8,
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MITS, 8,
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MRG0, 8,
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MRG1, 8,
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MRG2, 8,
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MRG3, 8,
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}
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Method(WACK, 0)
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{
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Store(0, Local0)
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While (LNotEqual(Local0, 0xFA)) {
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Store(MRG0, Local0)
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Sleep(10)
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}
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}
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//Init
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Method (ITZE, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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@ -1,64 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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//BTDC Due to IMC Fan, ACPI control codes
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCA,8
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}
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IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) {
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Offset(0x80),
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MSTI, 8,
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MITS, 8,
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MRG0, 8,
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MRG1, 8,
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MRG2, 8,
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MRG3, 8,
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}
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Method(WACK, 0)
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{
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Store(0, Local0)
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Store(50, Local1)
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While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) {
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Store(MRG0, Local0)
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Sleep(10)
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Decrement(Local1)
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}
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}
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//Init
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Method (ITZE, 0)
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{
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Store(0, MRG0)
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Store(0xB5, MRG1)
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Store(0, MRG2)
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Store(0x96, MSTI)
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WACK()
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Store(0, MRG0)
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Store(0, MRG1)
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Store(0, MRG2)
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Store(0x80, MSTI)
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WACK()
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Or(MRG2, 0x01, Local0)
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Store(0, MRG0)
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Store(0, MRG1)
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Store(Local0, MRG2)
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Store(0x81, MSTI)
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WACK()
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}
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@ -1,6 +1,8 @@
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/*
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/*
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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||||||
* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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* the Free Software Foundation; version 2 of the License.
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@ -11,7 +13,6 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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//BTDC Due to IMC Fan, ACPI control codes
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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OperationRegion(IMIO, SystemIO, 0x3E, 0x02)
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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Field(IMIO , ByteAcc, NoLock, Preserve) {
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IMCX,8,
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IMCX,8,
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