util/inteltool: Move Denverton definitions into their own header
So far all group and community definitions live in one big c file. This 2500 line file slowly grows to a size, where readability is lost. Also the definitions are not reusable in a potential libinteltool. This commit moved the Denverton definitions into its own header. Change-Id: I6ce672c24059b9f3a4a984766184066f14df3013 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38630 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christoph Pomaska <github@slrie.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johanna Schander
Patrick Georgi
parent
aff7d1f864
commit
7da602ff47
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@ -25,6 +25,7 @@
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#include "gpio_names/apollolake.h"
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#include "gpio_names/cannonlake.h"
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#include "gpio_names/denverton.h"
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#include "gpio_names/icelake.h"
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#include "gpio_names/lewisburg.h"
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#include "gpio_names/sunrise.h"
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@ -32,228 +33,6 @@
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#define SBBAR_SIZE (16 * MiB)
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#define PCR_PORT_SIZE (64 * KiB)
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static const char *const denverton_group_north_all_names[] = {
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"NORTH_ALL_GBE0_SDP0",
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"NORTH_ALL_GBE1_SDP0",
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"NORTH_ALL_GBE0_SDP1",
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"NORTH_ALL_GBE1_SDP1",
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"NORTH_ALL_GBE0_SDP2",
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"NORTH_ALL_GBE1_SDP2",
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"NORTH_ALL_GBE0_SDP3",
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"NORTH_ALL_GBE1_SDP3",
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"NORTH_ALL_GBE2_LED0",
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"NORTH_ALL_GBE2_LED1",
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"NORTH_ALL_GBE0_I2C_CLK",
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"NORTH_ALL_GBE0_I2C_DATA",
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"NORTH_ALL_GBE1_I2C_CLK",
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"NORTH_ALL_GBE1_I2C_DATA",
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"NORTH_ALL_NCSI_RXD0",
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"NORTH_ALL_NCSI_CLK_IN",
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"NORTH_ALL_NCSI_RXD1",
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"NORTH_ALL_NCSI_CRS_DV",
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"NORTH_ALL_NCSI_ARB_IN",
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"NORTH_ALL_NCSI_TX_EN",
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"NORTH_ALL_NCSI_TXD0",
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"NORTH_ALL_NCSI_TXD1",
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"NORTH_ALL_NCSI_ARB_OUT",
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"NORTH_ALL_GBE0_LED0",
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"NORTH_ALL_GBE0_LED1",
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"NORTH_ALL_GBE1_LED0",
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"NORTH_ALL_GBE1_LED1",
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"NORTH_ALL_GPIO_0",
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"NORTH_ALL_PCIE_CLKREQ0_N",
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"NORTH_ALL_PCIE_CLKREQ1_N",
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"NORTH_ALL_PCIE_CLKREQ2_N",
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"NORTH_ALL_PCIE_CLKREQ3_N",
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"NORTH_ALL_PCIE_CLKREQ4_N",
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"NORTH_ALL_GPIO_1",
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"NORTH_ALL_GPIO_2",
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"NORTH_ALL_SVID_ALERT_N",
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"NORTH_ALL_SVID_DATA",
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"NORTH_ALL_SVID_CLK",
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"NORTH_ALL_THERMTRIP_N",
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"NORTH_ALL_PROCHOT_N",
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"NORTH_ALL_MEMHOT_N",
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};
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static const struct gpio_group denverton_group_north_all = {
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.display = "------- GPIO Group North All -------",
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.pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_north_all_names,
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};
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static const struct gpio_group *const denverton_community_north_groups[] = {
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&denverton_group_north_all,
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};
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static const struct gpio_community denverton_community_north = {
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.name = "------- GPIO Community 0 -------",
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.pcr_port_id = 0xc2,
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.group_count = ARRAY_SIZE(denverton_community_north_groups),
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.groups = denverton_community_north_groups,
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};
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static const char *const denverton_group_south_dfx_names[] = {
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"SOUTH_DFX_DFX_PORT_CLK0",
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"SOUTH_DFX_DFX_PORT_CLK1",
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"SOUTH_DFX_DFX_PORT0",
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"SOUTH_DFX_DFX_PORT1",
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"SOUTH_DFX_DFX_PORT2",
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"SOUTH_DFX_DFX_PORT3",
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"SOUTH_DFX_DFX_PORT4",
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"SOUTH_DFX_DFX_PORT5",
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"SOUTH_DFX_DFX_PORT6",
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"SOUTH_DFX_DFX_PORT7",
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"SOUTH_DFX_DFX_PORT8",
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"SOUTH_DFX_DFX_PORT9",
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"SOUTH_DFX_DFX_PORT10",
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"SOUTH_DFX_DFX_PORT11",
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"SOUTH_DFX_DFX_PORT12",
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"SOUTH_DFX_DFX_PORT13",
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"SOUTH_DFX_DFX_PORT14",
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"SOUTH_DFX_DFX_PORT15",
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};
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static const struct gpio_group denverton_group_south_dfx = {
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.display = "------- GPIO Group South DFX -------",
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.pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_south_dfx_names,
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};
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static const char *const denverton_group_south_group0_names[] = {
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"SOUTH_GROUP0_GPIO_12",
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"SOUTH_GROUP0_SMB5_GBE_ALRT_N",
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"SOUTH_GROUP0_PCIE_CLKREQ5_N",
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"SOUTH_GROUP0_PCIE_CLKREQ6_N",
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"SOUTH_GROUP0_PCIE_CLKREQ7_N",
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"SOUTH_GROUP0_UART0_RXD",
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"SOUTH_GROUP0_UART0_TXD",
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"SOUTH_GROUP0_SMB5_GBE_CLK",
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"SOUTH_GROUP0_SMB5_GBE_DATA",
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"SOUTH_GROUP0_ERROR2_N",
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"SOUTH_GROUP0_ERROR1_N",
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"SOUTH_GROUP0_ERROR0_N",
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"SOUTH_GROUP0_IERR_N",
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"SOUTH_GROUP0_MCERR_N",
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"SOUTH_GROUP0_SMB0_LEG_CLK",
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"SOUTH_GROUP0_SMB0_LEG_DATA",
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"SOUTH_GROUP0_SMB0_LEG_ALRT_N",
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"SOUTH_GROUP0_SMB1_HOST_DATA",
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"SOUTH_GROUP0_SMB1_HOST_CLK",
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"SOUTH_GROUP0_SMB2_PECI_DATA",
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"SOUTH_GROUP0_SMB2_PECI_CLK",
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"SOUTH_GROUP0_SMB4_CSME0_DATA",
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"SOUTH_GROUP0_SMB4_CSME0_CLK",
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"SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
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"SOUTH_GROUP0_USB_OC0_N",
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"SOUTH_GROUP0_FLEX_CLK_SE0",
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"SOUTH_GROUP0_FLEX_CLK_SE1",
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"SOUTH_GROUP0_GPIO_4",
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"SOUTH_GROUP0_GPIO_5",
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"SOUTH_GROUP0_GPIO_6",
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"SOUTH_GROUP0_GPIO_7",
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"SOUTH_GROUP0_SATA0_LED_N",
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"SOUTH_GROUP0_SATA1_LED_N",
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"SOUTH_GROUP0_SATA_PDETECT0",
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"SOUTH_GROUP0_SATA_PDETECT1",
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"SOUTH_GROUP0_SATA0_SDOUT",
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"SOUTH_GROUP0_SATA1_SDOUT",
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"SOUTH_GROUP0_UART1_RXD",
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"SOUTH_GROUP0_UART1_TXD",
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"SOUTH_GROUP0_GPIO_8",
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"SOUTH_GROUP0_GPIO_9",
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"SOUTH_GROUP0_TCK",
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"SOUTH_GROUP0_TRST_N",
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"SOUTH_GROUP0_TMS",
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"SOUTH_GROUP0_TDI",
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"SOUTH_GROUP0_TDO",
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"SOUTH_GROUP0_CX_PRDY_N",
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"SOUTH_GROUP0_CX_PREQ_N",
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"SOUTH_GROUP0_CTBTRIGINOUT",
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"SOUTH_GROUP0_CTBTRIGOUT",
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"SOUTH_GROUP0_DFX_SPARE2",
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"SOUTH_GROUP0_DFX_SPARE3",
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"SOUTH_GROUP0_DFX_SPARE4",
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};
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static const struct gpio_group denverton_group_south_group0 = {
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.display = "------- GPIO Group South Group0 -------",
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.pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_south_group0_names,
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};
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static const char *const denverton_group_south_group1_names[] = {
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"SOUTH_GROUP1_SUSPWRDNACK",
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"SOUTH_GROUP1_PMU_SUSCLK",
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"SOUTH_GROUP1_ADR_TRIGGER",
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"SOUTH_GROUP1_PMU_SLP_S45_N",
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"SOUTH_GROUP1_PMU_SLP_S3_N",
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"SOUTH_GROUP1_PMU_WAKE_N",
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"SOUTH_GROUP1_PMU_PWRBTN_N",
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"SOUTH_GROUP1_PMU_RESETBUTTON_N",
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"SOUTH_GROUP1_PMU_PLTRST_N",
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"SOUTH_GROUP1_SUS_STAT_N",
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"SOUTH_GROUP1_SLP_S0IX_N",
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"SOUTH_GROUP1_SPI_CS0_N",
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"SOUTH_GROUP1_SPI_CS1_N",
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"SOUTH_GROUP1_SPI_MOSI_IO0",
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"SOUTH_GROUP1_SPI_MISO_IO1",
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"SOUTH_GROUP1_SPI_IO2",
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"SOUTH_GROUP1_SPI_IO3",
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"SOUTH_GROUP1_SPI_CLK",
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"SOUTH_GROUP1_SPI_CLK_LOOPBK",
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"SOUTH_GROUP1_ESPI_IO0",
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"SOUTH_GROUP1_ESPI_IO1",
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"SOUTH_GROUP1_ESPI_IO2",
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"SOUTH_GROUP1_ESPI_IO3",
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"SOUTH_GROUP1_ESPI_CS0_N",
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"SOUTH_GROUP1_ESPI_CLK",
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"SOUTH_GROUP1_ESPI_RST_N",
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"SOUTH_GROUP1_ESPI_ALRT0_N",
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"SOUTH_GROUP1_GPIO_10",
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"SOUTH_GROUP1_GPIO_11",
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"SOUTH_GROUP1_ESPI_CLK_LOOPBK",
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"SOUTH_GROUP1_EMMC_CMD",
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"SOUTH_GROUP1_EMMC_STROBE",
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"SOUTH_GROUP1_EMMC_CLK",
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"SOUTH_GROUP1_EMMC_D0",
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"SOUTH_GROUP1_EMMC_D1",
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"SOUTH_GROUP1_EMMC_D2",
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"SOUTH_GROUP1_EMMC_D3",
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"SOUTH_GROUP1_EMMC_D4",
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"SOUTH_GROUP1_EMMC_D5",
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"SOUTH_GROUP1_EMMC_D6",
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"SOUTH_GROUP1_EMMC_D7",
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"SOUTH_GROUP1_GPIO_3",
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};
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static const struct gpio_group denverton_group_south_group1 = {
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.display = "------- GPIO Group South Group1 -------",
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.pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
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.func_count = 1,
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.pad_names = denverton_group_south_group1_names,
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};
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static const struct gpio_group *const denverton_community_south_groups[] = {
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&denverton_group_south_dfx,
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&denverton_group_south_group0,
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&denverton_group_south_group1,
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};
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static const struct gpio_community denverton_community_south = {
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.name = "------- GPIO Community 1 -------",
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.pcr_port_id = 0xc5,
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.group_count = ARRAY_SIZE(denverton_community_south_groups),
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.groups = denverton_community_south_groups,
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};
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static const struct gpio_community *const denverton_communities[] = {
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&denverton_community_north, &denverton_community_south,
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};
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static const char *decode_pad_mode(const struct gpio_group *const group,
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const size_t pad, const uint32_t dw0)
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{
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@ -0,0 +1,229 @@
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#ifndef GPIO_NAMES_DENVERTON_H
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#define GPIO_NAMES_DENVERTON_H
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#include "gpio_groups.h"
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static const char *const denverton_group_north_all_names[] = {
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"NORTH_ALL_GBE0_SDP0",
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"NORTH_ALL_GBE1_SDP0",
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"NORTH_ALL_GBE0_SDP1",
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"NORTH_ALL_GBE1_SDP1",
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"NORTH_ALL_GBE0_SDP2",
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"NORTH_ALL_GBE1_SDP2",
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"NORTH_ALL_GBE0_SDP3",
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"NORTH_ALL_GBE1_SDP3",
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"NORTH_ALL_GBE2_LED0",
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"NORTH_ALL_GBE2_LED1",
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"NORTH_ALL_GBE0_I2C_CLK",
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"NORTH_ALL_GBE0_I2C_DATA",
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"NORTH_ALL_GBE1_I2C_CLK",
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"NORTH_ALL_GBE1_I2C_DATA",
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"NORTH_ALL_NCSI_RXD0",
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"NORTH_ALL_NCSI_CLK_IN",
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"NORTH_ALL_NCSI_RXD1",
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"NORTH_ALL_NCSI_CRS_DV",
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"NORTH_ALL_NCSI_ARB_IN",
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"NORTH_ALL_NCSI_TX_EN",
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"NORTH_ALL_NCSI_TXD0",
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"NORTH_ALL_NCSI_TXD1",
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"NORTH_ALL_NCSI_ARB_OUT",
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"NORTH_ALL_GBE0_LED0",
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"NORTH_ALL_GBE0_LED1",
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"NORTH_ALL_GBE1_LED0",
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"NORTH_ALL_GBE1_LED1",
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"NORTH_ALL_GPIO_0",
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"NORTH_ALL_PCIE_CLKREQ0_N",
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"NORTH_ALL_PCIE_CLKREQ1_N",
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"NORTH_ALL_PCIE_CLKREQ2_N",
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"NORTH_ALL_PCIE_CLKREQ3_N",
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"NORTH_ALL_PCIE_CLKREQ4_N",
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"NORTH_ALL_GPIO_1",
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"NORTH_ALL_GPIO_2",
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"NORTH_ALL_SVID_ALERT_N",
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"NORTH_ALL_SVID_DATA",
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"NORTH_ALL_SVID_CLK",
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"NORTH_ALL_THERMTRIP_N",
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"NORTH_ALL_PROCHOT_N",
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"NORTH_ALL_MEMHOT_N",
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};
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static const char *const denverton_group_south_dfx_names[] = {
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"SOUTH_DFX_DFX_PORT_CLK0",
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"SOUTH_DFX_DFX_PORT_CLK1",
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"SOUTH_DFX_DFX_PORT0",
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"SOUTH_DFX_DFX_PORT1",
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"SOUTH_DFX_DFX_PORT2",
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"SOUTH_DFX_DFX_PORT3",
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"SOUTH_DFX_DFX_PORT4",
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"SOUTH_DFX_DFX_PORT5",
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"SOUTH_DFX_DFX_PORT6",
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"SOUTH_DFX_DFX_PORT7",
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"SOUTH_DFX_DFX_PORT8",
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"SOUTH_DFX_DFX_PORT9",
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"SOUTH_DFX_DFX_PORT10",
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"SOUTH_DFX_DFX_PORT11",
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"SOUTH_DFX_DFX_PORT12",
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"SOUTH_DFX_DFX_PORT13",
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"SOUTH_DFX_DFX_PORT14",
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"SOUTH_DFX_DFX_PORT15",
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};
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static const char *const denverton_group_south_group0_names[] = {
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"SOUTH_GROUP0_GPIO_12",
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"SOUTH_GROUP0_SMB5_GBE_ALRT_N",
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"SOUTH_GROUP0_PCIE_CLKREQ5_N",
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"SOUTH_GROUP0_PCIE_CLKREQ6_N",
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"SOUTH_GROUP0_PCIE_CLKREQ7_N",
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"SOUTH_GROUP0_UART0_RXD",
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"SOUTH_GROUP0_UART0_TXD",
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"SOUTH_GROUP0_SMB5_GBE_CLK",
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"SOUTH_GROUP0_SMB5_GBE_DATA",
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"SOUTH_GROUP0_ERROR2_N",
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"SOUTH_GROUP0_ERROR1_N",
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"SOUTH_GROUP0_ERROR0_N",
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"SOUTH_GROUP0_IERR_N",
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"SOUTH_GROUP0_MCERR_N",
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"SOUTH_GROUP0_SMB0_LEG_CLK",
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"SOUTH_GROUP0_SMB0_LEG_DATA",
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"SOUTH_GROUP0_SMB0_LEG_ALRT_N",
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"SOUTH_GROUP0_SMB1_HOST_DATA",
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"SOUTH_GROUP0_SMB1_HOST_CLK",
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"SOUTH_GROUP0_SMB2_PECI_DATA",
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"SOUTH_GROUP0_SMB2_PECI_CLK",
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"SOUTH_GROUP0_SMB4_CSME0_DATA",
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"SOUTH_GROUP0_SMB4_CSME0_CLK",
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"SOUTH_GROUP0_SMB4_CSME0_ALRT_N",
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"SOUTH_GROUP0_USB_OC0_N",
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"SOUTH_GROUP0_FLEX_CLK_SE0",
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"SOUTH_GROUP0_FLEX_CLK_SE1",
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"SOUTH_GROUP0_GPIO_4",
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"SOUTH_GROUP0_GPIO_5",
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"SOUTH_GROUP0_GPIO_6",
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"SOUTH_GROUP0_GPIO_7",
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"SOUTH_GROUP0_SATA0_LED_N",
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"SOUTH_GROUP0_SATA1_LED_N",
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"SOUTH_GROUP0_SATA_PDETECT0",
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"SOUTH_GROUP0_SATA_PDETECT1",
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"SOUTH_GROUP0_SATA0_SDOUT",
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"SOUTH_GROUP0_SATA1_SDOUT",
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"SOUTH_GROUP0_UART1_RXD",
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"SOUTH_GROUP0_UART1_TXD",
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"SOUTH_GROUP0_GPIO_8",
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"SOUTH_GROUP0_GPIO_9",
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"SOUTH_GROUP0_TCK",
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"SOUTH_GROUP0_TRST_N",
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"SOUTH_GROUP0_TMS",
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"SOUTH_GROUP0_TDI",
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"SOUTH_GROUP0_TDO",
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"SOUTH_GROUP0_CX_PRDY_N",
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"SOUTH_GROUP0_CX_PREQ_N",
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"SOUTH_GROUP0_CTBTRIGINOUT",
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||||
"SOUTH_GROUP0_CTBTRIGOUT",
|
||||
"SOUTH_GROUP0_DFX_SPARE2",
|
||||
"SOUTH_GROUP0_DFX_SPARE3",
|
||||
"SOUTH_GROUP0_DFX_SPARE4",
|
||||
};
|
||||
|
||||
static const char *const denverton_group_south_group1_names[] = {
|
||||
"SOUTH_GROUP1_SUSPWRDNACK",
|
||||
"SOUTH_GROUP1_PMU_SUSCLK",
|
||||
"SOUTH_GROUP1_ADR_TRIGGER",
|
||||
"SOUTH_GROUP1_PMU_SLP_S45_N",
|
||||
"SOUTH_GROUP1_PMU_SLP_S3_N",
|
||||
"SOUTH_GROUP1_PMU_WAKE_N",
|
||||
"SOUTH_GROUP1_PMU_PWRBTN_N",
|
||||
"SOUTH_GROUP1_PMU_RESETBUTTON_N",
|
||||
"SOUTH_GROUP1_PMU_PLTRST_N",
|
||||
"SOUTH_GROUP1_SUS_STAT_N",
|
||||
"SOUTH_GROUP1_SLP_S0IX_N",
|
||||
"SOUTH_GROUP1_SPI_CS0_N",
|
||||
"SOUTH_GROUP1_SPI_CS1_N",
|
||||
"SOUTH_GROUP1_SPI_MOSI_IO0",
|
||||
"SOUTH_GROUP1_SPI_MISO_IO1",
|
||||
"SOUTH_GROUP1_SPI_IO2",
|
||||
"SOUTH_GROUP1_SPI_IO3",
|
||||
"SOUTH_GROUP1_SPI_CLK",
|
||||
"SOUTH_GROUP1_SPI_CLK_LOOPBK",
|
||||
"SOUTH_GROUP1_ESPI_IO0",
|
||||
"SOUTH_GROUP1_ESPI_IO1",
|
||||
"SOUTH_GROUP1_ESPI_IO2",
|
||||
"SOUTH_GROUP1_ESPI_IO3",
|
||||
"SOUTH_GROUP1_ESPI_CS0_N",
|
||||
"SOUTH_GROUP1_ESPI_CLK",
|
||||
"SOUTH_GROUP1_ESPI_RST_N",
|
||||
"SOUTH_GROUP1_ESPI_ALRT0_N",
|
||||
"SOUTH_GROUP1_GPIO_10",
|
||||
"SOUTH_GROUP1_GPIO_11",
|
||||
"SOUTH_GROUP1_ESPI_CLK_LOOPBK",
|
||||
"SOUTH_GROUP1_EMMC_CMD",
|
||||
"SOUTH_GROUP1_EMMC_STROBE",
|
||||
"SOUTH_GROUP1_EMMC_CLK",
|
||||
"SOUTH_GROUP1_EMMC_D0",
|
||||
"SOUTH_GROUP1_EMMC_D1",
|
||||
"SOUTH_GROUP1_EMMC_D2",
|
||||
"SOUTH_GROUP1_EMMC_D3",
|
||||
"SOUTH_GROUP1_EMMC_D4",
|
||||
"SOUTH_GROUP1_EMMC_D5",
|
||||
"SOUTH_GROUP1_EMMC_D6",
|
||||
"SOUTH_GROUP1_EMMC_D7",
|
||||
"SOUTH_GROUP1_GPIO_3",
|
||||
};
|
||||
|
||||
|
||||
static const struct gpio_group denverton_group_north_all = {
|
||||
.display = "------- GPIO Group North All -------",
|
||||
.pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1,
|
||||
.func_count = 1,
|
||||
.pad_names = denverton_group_north_all_names,
|
||||
};
|
||||
|
||||
static const struct gpio_group *const denverton_community_north_groups[] = {
|
||||
&denverton_group_north_all,
|
||||
};
|
||||
|
||||
static const struct gpio_community denverton_community_north = {
|
||||
.name = "------- GPIO Community 0 -------",
|
||||
.pcr_port_id = 0xc2,
|
||||
.group_count = ARRAY_SIZE(denverton_community_north_groups),
|
||||
.groups = denverton_community_north_groups,
|
||||
};
|
||||
|
||||
static const struct gpio_group denverton_group_south_dfx = {
|
||||
.display = "------- GPIO Group South DFX -------",
|
||||
.pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1,
|
||||
.func_count = 1,
|
||||
.pad_names = denverton_group_south_dfx_names,
|
||||
};
|
||||
|
||||
static const struct gpio_group denverton_group_south_group0 = {
|
||||
.display = "------- GPIO Group South Group0 -------",
|
||||
.pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1,
|
||||
.func_count = 1,
|
||||
.pad_names = denverton_group_south_group0_names,
|
||||
};
|
||||
|
||||
static const struct gpio_group denverton_group_south_group1 = {
|
||||
.display = "------- GPIO Group South Group1 -------",
|
||||
.pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1,
|
||||
.func_count = 1,
|
||||
.pad_names = denverton_group_south_group1_names,
|
||||
};
|
||||
|
||||
static const struct gpio_group *const denverton_community_south_groups[] = {
|
||||
&denverton_group_south_dfx,
|
||||
&denverton_group_south_group0,
|
||||
&denverton_group_south_group1,
|
||||
};
|
||||
|
||||
static const struct gpio_community denverton_community_south = {
|
||||
.name = "------- GPIO Community 1 -------",
|
||||
.pcr_port_id = 0xc5,
|
||||
.group_count = ARRAY_SIZE(denverton_community_south_groups),
|
||||
.groups = denverton_community_south_groups,
|
||||
};
|
||||
|
||||
static const struct gpio_community *const denverton_communities[] = {
|
||||
&denverton_community_north, &denverton_community_south,
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue