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device/pnp: remove struct io_info 

The 'set' field was not used anywhere. Replace the struct with a simple
integer representing the mask.

initializer updates performed with:
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04]? ?\}/0\1/g' \
	src/ec/*/*/ec.c
sed -i -r 's/\{ ?0(x([[:digit:]abcdefABCDEF]{3,4}))?, (0x)?[04] ?\}/0\1/g' \
	src/ec/*/*/ec_lpc.c \
	src/superio/*/*/superio.c \
	src/superio/smsc/fdc37n972/fdc37n972.c \
	src/superio/smsc/sio10n268/sio10n268.c \
	src/superio/via/vt1211/vt1211.c

src/ec/kontron/it8516e/ec.c was manually updated. The previous value for
IT8516E_LDN_SWUC appears to have been a typo, as it was out of range and
had a zero bit in the middle of the mask.

Change-Id: I1e7853844605cd2a6d568caf05488e1218fb53f9
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/20078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Samuel Holland 2017-06-06 22:55:01 -05:00 committed by Patrick Georgi
parent c21ba2cd3e
commit 7daac91236
67 changed files with 378 additions and 382 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/device/pnp_device.c
View File

@ -191,12 +191,12 @@ struct device_operations pnp_ops = {
/* PNP chip operations */
static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info)
static void pnp_get_ioresource(device_t dev, u8 index, u16 mask)
{
struct resource *resource;
unsigned moving, gran, step;
if (!info->mask) {
if (!mask) {
printk(BIOS_ERR, "ERROR: device %s index %d has no mask.\n",
dev_path(dev), index);
return;
@ -210,7 +210,7 @@ static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info)
/* Get the resource size... */
moving = info->mask;
moving = mask;
gran = 15;
step = 1 << gran;
@ -238,7 +238,7 @@ static void pnp_get_ioresource(device_t dev, u8 index, struct io_info *info)
/* Set the resource size and alignment. */
resource->gran = gran;
resource->align = gran;
resource->limit = info->mask | (step - 1);
resource->limit = mask | (step - 1);
resource->size = 1 << gran;
}
@ -247,13 +247,13 @@ static void get_resources(device_t dev, struct pnp_info *info)
struct resource *resource;
if (info->flags & PNP_IO0)
pnp_get_ioresource(dev, PNP_IDX_IO0, &info->io0);
pnp_get_ioresource(dev, PNP_IDX_IO0, info->io0);
if (info->flags & PNP_IO1)
pnp_get_ioresource(dev, PNP_IDX_IO1, &info->io1);
pnp_get_ioresource(dev, PNP_IDX_IO1, info->io1);
if (info->flags & PNP_IO2)
pnp_get_ioresource(dev, PNP_IDX_IO2, &info->io2);
pnp_get_ioresource(dev, PNP_IDX_IO2, info->io2);
if (info->flags & PNP_IO3)
pnp_get_ioresource(dev, PNP_IDX_IO3, &info->io3);
pnp_get_ioresource(dev, PNP_IDX_IO3, info->io3);
if (info->flags & PNP_IRQ0) {
resource = new_resource(dev, PNP_IDX_IRQ0);

2
src/ec/compal/ene932/ec.c
View File

@ -144,7 +144,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, 0, 0, { 0, 0 }, }
{ &ops, 0, 0, 0, }
};
static void enable_dev(struct device *dev)

2
src/ec/google/chromeec/ec_lpc.c
View File

@ -471,7 +471,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, 0, 0, { 0, 0 }, }
{ &ops, 0, 0, 0, }
};
static void enable_dev(struct device *dev)

18
src/ec/kontron/it8516e/ec.c
View File

@ -235,16 +235,16 @@ static struct device_operations it8516e_pm2_ops = {
};
static struct pnp_info it8516e_dev_infos[] = {
{ NULL, IT8516E_LDN_UART1, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, },
{ NULL, IT8516E_LDN_UART2, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, },
{ NULL, IT8516E_LDN_SWUC, PNP_IO0 | PNP_IRQ0, { 0xff7e0, }, },
{ NULL, IT8516E_LDN_UART1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, IT8516E_LDN_UART2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ NULL, IT8516E_LDN_SWUC, PNP_IO0 | PNP_IRQ0, 0xffe0, },
{ NULL, IT8516E_LDN_MOUSE, PNP_IRQ0, },
{ NULL, IT8516E_LDN_KBD, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, },
{ NULL, IT8516E_LDN_SMFI, PNP_IO0 | PNP_IRQ0, { 0xfff0, }, },
{ NULL, IT8516E_LDN_BRAM, PNP_IO0 | PNP_IO1, { 0xfffe, }, { 0xfffe, }, },
{ NULL, IT8516E_LDN_PM1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, },
{ &it8516e_pm2_ops, IT8516E_LDN_PM2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, },
{ NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, },
{ NULL, IT8516E_LDN_KBD, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
{ NULL, IT8516E_LDN_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ NULL, IT8516E_LDN_BRAM, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, },
{ NULL, IT8516E_LDN_PM1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
{ &it8516e_pm2_ops, IT8516E_LDN_PM2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
{ NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
};
static void it8516e_enable(struct device *dev)

2
src/ec/quanta/ene_kb3940q/ec.c
View File

@ -154,7 +154,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, 0, 0, { 0, 0 }, }
{ &ops, 0, 0, 0, }
};
static void enable_dev(struct device *dev)

2
src/ec/quanta/it8518/ec.c
View File

@ -167,7 +167,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, 0, 0, { 0, 0 }, }
{ &ops, 0, 0, 0, }
};
static void enable_dev(struct device *dev)

2
src/ec/roda/it8518/ec.c
View File

@ -53,7 +53,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, 0, 0, { 0, 0 }, }
{ &ops, 0, 0, 0, }
};
static void enable_dev(struct device *dev)

6
src/include/device/pnp.h
View File

@ -30,10 +30,6 @@ extern struct device_operations pnp_ops;
/* PNP helper operations */
struct io_info {
unsigned int mask, set;
};
struct pnp_info {
struct device_operations *ops;
unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */
@ -62,7 +58,7 @@ struct pnp_info {
#define PNP_MSCC 0x200000
#define PNP_MSCD 0x400000
#define PNP_MSCE 0x800000
struct io_info io0, io1, io2, io3;
u16 io0, io1, io2, io3;
};
struct resource *pnp_get_resource(device_t dev, unsigned int index);
void pnp_enable_devices(struct device *dev, struct device_operations *ops,

10
src/superio/fintek/f71805f/superio.c
View File

@ -41,11 +41,11 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, F71805F_GPIO, PNP_IRQ0, },
{ &ops, F71805F_PME, },
};

10
src/superio/fintek/f71808a/superio.c
View File

@ -54,12 +54,12 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71808A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71808A_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71808A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71808A_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71808A_HWM, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71808A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F71808A_GPIO, PNP_IRQ0, },
{ &ops, F71808A_WDT, PNP_IO0, {0x07f8, 0},},
{ &ops, F71808A_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71808A_WDT, PNP_IO0, 0x07f8,},
{ &ops, F71808A_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71808A_PME, },
};

2
src/superio/fintek/f71859/superio.c
View File

@ -42,7 +42,7 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

14
src/superio/fintek/f71863fg/superio.c
View File

@ -50,14 +50,14 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F71863FG_GPIO, },
{ &ops, F71863FG_VID, PNP_IO0, {0x07f8, 0}, },
{ &ops, F71863FG_VID, PNP_IO0, 0x07f8, },
{ &ops, F71863FG_SPI, },
{ &ops, F71863FG_PME, },
};

14
src/superio/fintek/f71869ad/superio.c
View File

@ -106,15 +106,15 @@ static struct device_operations ops = {
*
*/
static struct pnp_info pnp_dev_info[] = {
{ &ops, F71869AD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71869AD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71869AD_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71869AD_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71869AD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F71869AD_GPIO, },
{ &ops, F71869AD_WDT, },
{ &ops, F71869AD_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71869AD_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71869AD_PME, },
};

14
src/superio/fintek/f71872/superio.c
View File

@ -48,14 +48,14 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x07f8 etc. values may not be correct. */
{ &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, },
{ &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F71872_GPIO, PNP_IRQ0, },
{ &ops, F71872_VID, PNP_IO0, {0x0ff8, 0}, },
{ &ops, F71872_VID, PNP_IO0, 0x0ff8, },
{ &ops, F71872_PM, },
};

8
src/superio/fintek/f81216h/superio.c
View File

@ -94,10 +94,10 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, F81216H_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F81216H_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F81216H_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F81216H_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, F81216H_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F81216H_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F81216H_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F81216H_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, F81216H_WDT, },
};

12
src/superio/fintek/f81865f/superio.c
View File

@ -48,12 +48,12 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
{ &ops, F81865F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F81865F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81865F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81865F_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, },
{ &ops, F81865F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F81865F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
{ &ops, F81865F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F81865F_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81865F_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81865F_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F81865F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F81865F_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, },
{ &ops, F81865F_GPIO, PNP_IRQ0, },
{ &ops, F81865F_PME, },
};

20
src/superio/fintek/f81866d/superio.c
View File

@ -70,16 +70,16 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* TODO: Some of the 0x7f8 etc. values may not be correct. */
{ &ops, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F81866D_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81866D_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81866D_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81866D_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81866D_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81866D_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, },
{ &ops, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, F81866D_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, },
{ &ops, F81866D_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F81866D_SP1, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81866D_SP2, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81866D_SP3, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81866D_SP4, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81866D_SP5, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81866D_SP6, PNP_IO0 | PNP_IRQ0, 0x7f8, },
{ &ops, F81866D_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, },
{ &ops, F81866D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, F81866D_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, },
{ &ops, F81866D_GPIO, PNP_IRQ0, },
{ &ops, F81866D_PME, },
{ &ops, F81866D_WDT, },

4
src/superio/intel/i3100/superio.c
View File

@ -53,8 +53,8 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

6
src/superio/intel/i8900/superio.c
View File

@ -70,9 +70,9 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, I8900_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, I8900_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, I8900_WDT, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, I8900_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, I8900_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, I8900_WDT, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

6
src/superio/ite/it8671f/superio.c
View File

@ -49,9 +49,9 @@ static struct device_operations ops = {
/* TODO: FDC, PP, KBCM. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)

20
src/superio/ite/it8712f/superio.c
View File

@ -62,17 +62,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ffc, 0}, },
{ &ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, },
{ &ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0fff, 0}, {0x0fff, 4}, },
{ &ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ffc, },
{ &ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, },
{ &ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, },
{ &ops, IT8712F_KBCM, PNP_IRQ0, },
{ &ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0x0fff, 0}, {0x0ff8, 0}, {0x0ff8, 0}, },
{ &ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_GAME, PNP_IO0, {0x0fff, 0}, },
{ &ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, 0x0fff, 0x0ff8, 0x0ff8, },
{ &ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, IT8712F_GAME, PNP_IO0, 0x0fff, },
{ &ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

18
src/superio/ite/it8716f/superio.c
View File

@ -75,16 +75,16 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, },
{ &ops, IT8716F_KBCM, PNP_IRQ0, },
{ &ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x07f8, 0}, {0x07f8, 0}, },
{ &ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x07fe, 4}, },
{ &ops, IT8716F_GAME, PNP_IO0, {0x07ff, 0}, },
{ &ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, 0, 0x07f8, 0x07f8, },
{ &ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ &ops, IT8716F_GAME, PNP_IO0, 0x07ff, },
{ &ops, IT8716F_IR, },
};

12
src/superio/ite/it8718f/superio.c
View File

@ -64,18 +64,18 @@ static struct device_operations ops = {
/* TODO: IR. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8718F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0
| PNP_MSC0 | PNP_MSC1, {0x0ff8, 0}, },
{ &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
| PNP_MSC0 | PNP_MSC1, 0x0ff8, },
{ &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, IT8718F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0
| PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3
| PNP_MSC4 | PNP_MSC5 | PNP_MSC6,
{0x0ff8, 0}, {0x0ff8, 4}, },
0x0ff8, 0x0ff8, },
{ &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0
| PNP_MSC0, {0x07f8, 0}, {0x07f8, 4}, },
| PNP_MSC0, 0x07f8, 0x07f8, },
{ &ops, IT8718F_KBCM, PNP_IRQ0 | PNP_MSC0, },
{ &ops, IT8718F_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0
| PNP_DRQ0 | PNP_MSC0, {0x0ff8, 0}, {0x0ff8, 4}, },
| PNP_DRQ0 | PNP_MSC0, 0x0ff8, 0x0ff8, },
};
static void enable_dev(struct device *dev)

16
src/superio/ite/it8720f/superio.c
View File

@ -60,33 +60,33 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8720F_FDC,
PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, IT8720F_SP1,
PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, IT8720F_SP2,
PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, IT8720F_PP,
PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0,
{0x0ff8, 0}, {0x0ffc, 0}, },
0x0ff8, 0x0ffc, },
{ &ops, IT8720F_EC,
PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6,
{0x0ff8, 0}, {0x0ffc, 0}, },
0x0ff8, 0x0ffc, },
{ &ops, IT8720F_KBCK,
PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
{0x0fff, 0}, {0x0fff, 0}, },
0x0fff, 0x0fff, },
{ &ops, IT8720F_KBCM,
PNP_IRQ0 | PNP_MSC0, },
{ &ops, IT8720F_GPIO,
PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCD | PNP_MSCE,
{0x0ff8, 0}, {0x0ff8, 0}, {0x0ff8, 0}, },
0x0ff8, 0x0ff8, 0x0ff8, },
{ &ops, IT8720F_CIR,
PNP_IO0 | PNP_IRQ0 | PNP_MSC0,
{0x0ff8, 0}, },
0x0ff8, },
};
static void enable_dev(struct device *dev)

6
src/superio/ite/it8721f/superio.c
View File

@ -54,9 +54,9 @@ static struct device_operations ops = {
/* TODO: FDC, PP, EC, KBCM, IR. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8721F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, IT8721F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, IT8721F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, IT8721F_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, IT8721F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, IT8721F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)

16
src/superio/ite/it8728f/superio.c
View File

@ -59,15 +59,15 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, IT8728F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, IT8728F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8728F_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8728F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ffc, 0}, },
{ &ops, IT8728F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, },
{ &ops, IT8728F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0fff, 0}, {0x0fff, 4}, },
{ &ops, IT8728F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, IT8728F_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, IT8728F_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, IT8728F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ffc, },
{ &ops, IT8728F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, },
{ &ops, IT8728F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, },
{ &ops, IT8728F_KBCM, PNP_IRQ0, },
{ &ops, IT8728F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0x0fff, 0}, {0x0ff8, 0}, {0x0ff8, 0}, },
{ &ops, IT8728F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8728F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, 0x0fff, 0x0ff8, 0x0ff8, },
{ &ops, IT8728F_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

12
src/superio/ite/it8772f/superio.c
View File

@ -267,23 +267,23 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* Floppy Disk Controller */
{ &ops, IT8772F_FDC, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8772F_FDC, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
/* Serial Port 1 */
{ &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
/* Environmental Controller */
{ &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 |
PNP_MSC4 | PNP_MSCA,
{0x0ff8, 0}, {0x0ffc, 4}, },
0x0ff8, 0x0ffc, },
/* KBC Keyboard */
{ &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
{0x0fff, 0}, {0x0fff, 4}, },
0x0fff, 0x0fff, },
/* KBC Mouse */
{ &ops, IT8772F_KBCM, PNP_IRQ0, },
/* 27 GPIOs */
{ &ops, IT8772F_GPIO, PNP_IO0 | PNP_IO1,
{0x0fff, 0}, {0x0ff8, 0}, },
0x0fff, 0x0ff8, },
/* Infrared */
{ &ops, IT8772F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, IT8772F_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

24
src/superio/ite/it8783ef/superio.c
View File

@ -59,23 +59,23 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
/* Floppy Disk Controller */
{ &ops, IT8783EF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
{0x0ff8, 0}, },
0x0ff8, },
/* Serial Port 1 */
{ &ops, IT8783EF_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
/* Serial Port 2 */
{ &ops, IT8783EF_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
/* Printer Port */
{ &ops, IT8783EF_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 |
PNP_MSC0,
{0x0ffc, 0}, {0x0ffc, 0}, },
0x0ffc, 0x0ffc, },
/* Environmental Controller */
{ &ops, IT8783EF_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 |
PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 |
PNP_MSC5 | PNP_MSC6 | PNP_MSC7,
{0x0ff8, 0}, {0x0ff8, 0}, },
0x0ff8, 0x0ff8, },
/* KBC Keyboard */
{ &ops, IT8783EF_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
{0x0fff, 0}, {0x0fff, 0}, },
0x0fff, 0x0fff, },
/* KBC Mouse */
{ &ops, IT8783EF_KBCM, PNP_IRQ0 | PNP_MSC0, },
/* GPIO */
@ -83,17 +83,17 @@ static struct pnp_info pnp_dev_info[] = {
PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 |
PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB,
{0x0ffc, 0}, {0x0fff, 0}, {0x0ff8, 0}, },
0x0ffc, 0x0fff, 0x0ff8, },
/* Serial Port 3 */
{ &ops, IT8783EF_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
/* Serial Port 4 */
{ &ops, IT8783EF_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
/* Serial Port 5 */
{ &ops, IT8783EF_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
/* Serial Port 6 */
{ &ops, IT8783EF_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
/* Consumer Infrared */
{ &ops, IT8783EF_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x0ff8, 0}, },
{ &ops, IT8783EF_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

10
src/superio/nsc/pc87309/superio.c
View File

@ -43,13 +43,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ &ops, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ &ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
/* TODO: PM. */
{ &ops, PC87309_KBCM, PNP_IRQ0, },
{ &ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x7f8, 4}, },
{ &ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x7f8, },
};
static void enable_dev(struct device *dev)

20
src/superio/nsc/pc87360/superio.c
View File

@ -45,17 +45,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ &ops, PC87360_KBCM, PNP_IRQ0, },
{ &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
{ &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
};
static void enable_dev(struct device *dev)

20
src/superio/nsc/pc87366/superio.c
View File

@ -45,17 +45,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ &ops, PC87366_KBCM, PNP_IRQ0, },
{ &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
{ &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc, },
};
static void enable_dev(struct device *dev)

8
src/superio/nsc/pc87382/superio.c
View File

@ -46,10 +46,10 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x07f8, 0 } },
{ &ops, PC87382_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
{ &ops, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
{ &ops, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0 } },
{ &ops, PC87382_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 },
{ &ops, PC87382_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
{ &ops, PC87382_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
{ &ops, PC87382_DOCK, PNP_IO0 | PNP_IRQ0, 0xfffe },
};
static void enable_dev(struct device *dev)

8
src/superio/nsc/pc87384/superio.c
View File

@ -31,10 +31,10 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} },
{ &ops, PC87384_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
{ &ops, PC87384_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 } },
{ &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } },
{ &ops, PC87384_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8 },
{ &ops, PC87384_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
{ &ops, PC87384_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8 },
{ &ops, PC87384_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0 },
};
static void enable_dev(struct device *dev)

12
src/superio/nsc/pc87392/superio.c
View File

@ -37,12 +37,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0} },
{ &ops, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0} },
{ &ops, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0} },
{ &ops, PC87392_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0} },
{ &ops, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0} },
{ &ops, PC87392_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0} },
{ &ops, PC87392_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa },
{ &ops, PC87392_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8 },
{ &ops, PC87392_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8 },
{ &ops, PC87392_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8 },
{ &ops, PC87392_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8 },
{ &ops, PC87392_WDT, PNP_IO0 | PNP_IRQ0, 0xfffc },
};
static void enable_dev(struct device *dev)

18
src/superio/nsc/pc87417/superio.c
View File

@ -46,16 +46,16 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ &ops, PC87417_KBCM, PNP_IRQ0, },
{ &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, },
{ &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, {0xfffe, 0}, {0xfffe, 4}, },
{ &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, 0xffe0, },
{ &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, 0xfffe, 0xfffe, },
};
static void enable_dev(struct device *dev)

16
src/superio/nsc/pc97317/superio.c
View File

@ -49,15 +49,15 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffb, 0}, {0x0ffb, 4}, },
{ &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffb, 0x0ffb, },
{ &ops, PC97317_KBCM, PNP_IRQ0, },
{ &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, {0xfffe, 0}, },
{ &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xfffa, 0}, },
{ &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x03fc, 0}, },
{ &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0xfff8, 0}, },
{ &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, PC97317_GPIO, PNP_IO0, {0xfff8, 0}, },
{ &ops, PC97317_PM, PNP_IO0, {0xfffe, 0}, },
{ &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, 0xfffe, },
{ &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xfffa, },
{ &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x03fc, },
{ &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0xfff8, },
{ &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, 0xfff8, },
{ &ops, PC97317_GPIO, PNP_IO0, 0xfff8, },
{ &ops, PC97317_PM, PNP_IO0, 0xfffe, },
};
static void enable_dev(struct device *dev)

10
src/superio/nuvoton/nct5104d/superio.c
View File

@ -147,11 +147,11 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT5104D_FDC, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_FDC, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, NCT5104D_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, NCT5104D_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, NCT5104D_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, NCT5104D_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, NCT5104D_GPIO_WDT},
{ &ops, NCT5104D_GPIO_PP_OD},
{ &ops, NCT5104D_GPIO0},

12
src/superio/nuvoton/nct5572d/superio.c
View File

@ -96,16 +96,16 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT5572D_FDC}, /* no pins, removed from datasheet */
{ &ops, NCT5572D_PP}, /* no pins, removed from datasheet */
{ &ops, NCT5572D_SP1, PNP_IO0 | PNP_IRQ0, {0x0FF8, 0}, },
{ &ops, NCT5572D_IR, PNP_IO0 | PNP_IRQ0, {0x0FF8, 0}, },
{ &ops, NCT5572D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0FFF, 0}, {0x0FFF, 4}, },
{ &ops, NCT5572D_CIR, PNP_IO0 | PNP_IRQ0, {0x0FF8, 0}, },
{ &ops, NCT5572D_SP1, PNP_IO0 | PNP_IRQ0, 0x0FF8, },
{ &ops, NCT5572D_IR, PNP_IO0 | PNP_IRQ0, 0x0FF8, },
{ &ops, NCT5572D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0FFF, 0x0FFF, },
{ &ops, NCT5572D_CIR, PNP_IO0 | PNP_IRQ0, 0x0FF8, },
{ &ops, NCT5572D_WDT1},
{ &ops, NCT5572D_ACPI},
{ &ops, NCT5572D_HWM_TSI_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0FFE, 0}, {0x0FFE, 4}, },
{ &ops, NCT5572D_HWM_TSI_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0FFE, 0x0FFE, },
{ &ops, NCT5572D_PECI},
{ &ops, NCT5572D_SUSLED},
{ &ops, NCT5572D_CIRWKUP, PNP_IO0 | PNP_IRQ0, {0x0FF8, 0}, },
{ &ops, NCT5572D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0FF8, },
{ &ops, NCT5572D_GPIO_PP_OD},
{ &ops, NCT5572D_GPIO2},
{ &ops, NCT5572D_GPIO3},

18
src/superio/nuvoton/nct6776/superio.c
View File

@ -51,30 +51,30 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
{0x0fff, 0}, {0x0fff, 4}, },
0x0fff, 0x0fff, },
{ &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_ACPI},
{ &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
{0x0ffe, 0}, {0x0ffe, 4}, },
0x0ffe, 0x0ffe, },
{ &ops, NCT6776_VID},
{ &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_GPIO_PP_OD},
{ &ops, NCT6776_SVID},
{ &ops, NCT6776_DSLP},
{ &ops, NCT6776_GPIOA_LDN},
{ &ops, NCT6776_WDT1},
{ &ops, NCT6776_GPIOBASE, PNP_IO0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6776_GPIO0},
{ &ops, NCT6776_GPIO1},
{ &ops, NCT6776_GPIO2},

16
src/superio/nuvoton/nct6779d/superio.c
View File

@ -50,19 +50,19 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, },
{ &ops, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, NCT6779D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, },
{ &ops, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, NCT6779D_ACPI},
{ &ops, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffe, 0}, {0x0ffe, 4}, },
{ &ops, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ffe, 0x0ffe, },
{ &ops, NCT6779D_WDT1},
{ &ops, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, NCT6779D_GPIO_PP_OD},
{ &ops, NCT6779D_PRT80},
{ &ops, NCT6779D_DSLP},
{ &ops, NCT6779D_GPIOBASE, PNP_IO0, {0x0ff8, 0}, },
{ &ops, NCT6779D_GPIOBASE, PNP_IO0, 0x0ff8, },
{ &ops, NCT6779D_GPIO0},
{ &ops, NCT6779D_GPIO1},
{ &ops, NCT6779D_GPIO2},

16
src/superio/nuvoton/nct6791d/superio.c
View File

@ -51,27 +51,27 @@ static struct device_operations ops = {
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT6791D_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6791D_SP1, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6791D_SP2, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6791D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
{0x0fff, 0}, {0x0fff, 4}, },
0x0fff, 0x0fff, },
{ &ops, NCT6791D_CIR, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6791D_ACPI},
{ &ops, NCT6791D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
{0x0ffe, 0}, {0x0ffe, 4}, },
0x0ffe, 0x0ffe, },
{ &ops, NCT6791D_BCLK_WDT2_WDTMEM},
{ &ops, NCT6791D_CIRWUP, PNP_IO0 | PNP_IRQ0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6791D_GPIO_PP_OD},
{ &ops, NCT6791D_PORT80},
{ &ops, NCT6791D_WDT1},
{ &ops, NCT6791D_WDTMEM},
{ &ops, NCT6791D_GPIOBASE, PNP_IO0,
{0x0ff8, 0}, },
0x0ff8, },
{ &ops, NCT6791D_GPIO0},
{ &ops, NCT6791D_GPIO1},
{ &ops, NCT6791D_GPIO2},

6
src/superio/nuvoton/wpcm450/superio.c
View File

@ -45,9 +45,9 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, WPCM450_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, WPCM450_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, WPCM450_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, WPCM450_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, WPCM450_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, WPCM450_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)

2
src/superio/renesas/m3885x/superio.c
View File

@ -54,7 +54,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, 0, 0, { 0, 0 }, }
{ &ops, 0, 0, 0, }
};
static void enable_dev(struct device *dev)

12
src/superio/smsc/dme1737/superio.c
View File

@ -50,12 +50,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, DME1737_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, DME1737_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, DME1737_RT, PNP_IO0, {0x0780, 0}, },
{ &ops, DME1737_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, DME1737_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, DME1737_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, DME1737_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, DME1737_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, DME1737_RT, PNP_IO0, 0x0780, },
};
static void enable_dev(struct device *dev)

6
src/superio/smsc/fdc37n972/fdc37n972.c
View File

@ -46,9 +46,9 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)

2
src/superio/smsc/kbc1100/superio.c
View File

@ -45,7 +45,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, KBC1100_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x7ff, 0x7ff, },
};
static void enable_dev(struct device *dev)

12
src/superio/smsc/lpc47b272/superio.c
View File

@ -61,12 +61,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LPC47B272_RT, PNP_IO0, {0x0780, 0}, },
{ &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, LPC47B272_RT, PNP_IO0, 0x0780, },
};
/**

14
src/superio/smsc/lpc47b397/superio.c
View File

@ -135,13 +135,13 @@ static struct device_operations ops_hwm = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, },
{ &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, },
{ &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, },
{ &ops, LPC47B397_RT, PNP_IO0, 0x0780, },
};
static void enable_dev(struct device *dev)

12
src/superio/smsc/lpc47m10x/superio.c
View File

@ -59,12 +59,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LPC47M10X2_PME, PNP_IO0, { 0x0f80, 0 }, },
{ &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, LPC47M10X2_PME, PNP_IO0, 0x0f80, },
};
/**

10
src/superio/smsc/lpc47m15x/superio.c
View File

@ -45,11 +45,11 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
};
static void enable_dev(struct device *dev)

6
src/superio/smsc/lpc47n217/superio.c
View File

@ -57,9 +57,9 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }
{ &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }
};
/**

8
src/superio/smsc/lpc47n227/superio.c
View File

@ -55,10 +55,10 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
};
/**

14
src/superio/smsc/mec1308/superio.c
View File

@ -49,13 +49,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, MEC1308_PM1, PNP_IO0, { 0x7ff, 0 } },
{ &ops, MEC1308_EC1, PNP_IO0, { 0x7ff, 0 } },
{ &ops, MEC1308_EC2, PNP_IO0, { 0x7ff, 0 } },
{ &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, MEC1308_KBC, PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ },
{ &ops, MEC1308_EC0, PNP_IO0, { 0x7ff, 0 } },
{ &ops, MEC1308_MBX, PNP_IO0, { 0x7ff, 0 } },
{ &ops, MEC1308_PM1, PNP_IO0, 0x7ff },
{ &ops, MEC1308_EC1, PNP_IO0, 0x7ff },
{ &ops, MEC1308_EC2, PNP_IO0, 0x7ff },
{ &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, MEC1308_KBC, PNP_IRQ0, 0 /* IO Fixed at 0x60/0x64 */ },
{ &ops, MEC1308_EC0, PNP_IO0, 0x7ff },
{ &ops, MEC1308_MBX, PNP_IO0, 0x7ff },
};
static void enable_dev(struct device *dev)

2
src/superio/smsc/sch4037/superio.c
View File

@ -48,7 +48,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x7ff, 0x7ff, },
};
static void enable_dev(struct device *dev)

2
src/superio/smsc/sio1036/superio.c
View File

@ -41,7 +41,7 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, SIO1036_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

2
src/superio/smsc/sio10n268/sio10n268.c
View File

@ -47,7 +47,7 @@ static struct device_operations ops = {
/* TODO: FDC, PP, AUX. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, 0x07f8, 0x07f8, },
};
static void enable_dev(struct device *dev)

14
src/superio/smsc/smscsuperio/superio.c
View File

@ -194,19 +194,19 @@ static struct device_operations ops = {
* TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet).
*/
static struct pnp_info pnp_dev_info[] = {
{ &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, LD_RTC, },
{ &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, LD_AUX, },
{ &ops, LD_XBUS, },
{ &ops, LD_HWM, PNP_IO0, {0x07f0, 0}, },
{ &ops, LD_HWM, PNP_IO0, 0x07f0, },
{ &ops, LD_GAME, },
{ &ops, LD_PME, },
{ &ops, LD_MPU401, },
{ &ops, LD_RT, PNP_IO0, {0x0780, 0}, },
{ &ops, LD_RT, PNP_IO0, 0x0780, },
{ &ops, LD_ACPI, },
{ &ops, LD_SMB, },
};

22
src/superio/via/vt1211/vt1211.c
View File

@ -167,17 +167,17 @@ struct device_operations ops = {
/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */
static struct pnp_info pnp_dev_info[] = {
{ &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, },
{ &ops, VT1211_GAME, PNP_IO0, {0xfff8, 0}, },
{ &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, },
{ &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, {0xff00, 0}, },
{ &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff00, 0}, },
{ &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, 0xfffc, },
{ &ops, VT1211_GAME, PNP_IO0, 0xfff8, },
{ &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, 0xfff0, },
{ &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, 0xff00, },
{ &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0xff00, },
{ &ops, VT1211_ROM, },
};

14
src/superio/winbond/w83627dhg/superio.c
View File

@ -58,12 +58,12 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627DHG_SPI, PNP_IO1, {}, { 0x7f8, 0 }, },
{ &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627DHG_SPI, PNP_IO1, 0, 0x7f8, },
{ &ops, W83627DHG_GPIO6, },
{ &ops, W83627DHG_WDTO_PLED, },
{ &ops, W83627DHG_GPIO2, },
@ -71,7 +71,7 @@ static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627DHG_GPIO4, },
{ &ops, W83627DHG_GPIO5, },
{ &ops, W83627DHG_ACPI, PNP_IRQ0, },
{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
{ &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ &ops, W83627DHG_PECI_SST, },
};

18
src/superio/winbond/w83627ehg/superio.c
View File

@ -122,18 +122,18 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627EHG_WDTO_PLED, },
{ &ops, W83627EHG_ACPI, PNP_IRQ0, },
{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, },
{ &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, 0x07fe, },
{ &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, },
{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, },
{ &ops, W83627EHG_GAME, PNP_IO0, 0x07ff, },
{ &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, 0, 0x07fe, },
{ &ops, W83627EHG_GPIO1, },
{ &ops, W83627EHG_GPIO2, },
{ &ops, W83627EHG_GPIO3, },

16
src/superio/winbond/w83627hf/superio.c
View File

@ -129,17 +129,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83627HF_GPIO2, },
{ &ops, W83627HF_GPIO3, },
{ &ops, W83627HF_ACPI, },
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

14
src/superio/winbond/w83627thg/superio.c
View File

@ -48,16 +48,16 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, {0x07f8, 0}, },
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, 0x07f8, },
{ &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, 0x07ff, 0x07ff, },
{ &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83627THG_GPIO2, },
{ &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, },
{ &ops, W83627THG_ACPI, PNP_IRQ0, },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

20
src/superio/winbond/w83627uhg/superio.c
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@ -94,21 +94,21 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_GPIO3_4, },
{ &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
{ &ops, W83627UHG_GPIO1_2, },
{ &ops, W83627UHG_ACPI, PNP_IRQ0, },
{ &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, W83627UHG_PECI_SST, },
{ &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, 0x07f8, },
};
static void enable_dev(struct device *dev)

14
src/superio/winbond/w83667hg-a/superio.c
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@ -94,15 +94,15 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, },
{ &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, },
{ &ops, W83667HG_A_SPI1, PNP_IO1, {}, {0x0ff8, 0}},
{ &ops, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
{ &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
{ &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, },
{ &ops, W83667HG_A_SPI1, PNP_IO1, 0, 0x0ff8},
{ &ops, W83667HG_A_WDT1},
{ &ops, W83667HG_A_ACPI},
{ &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, },
{ &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, 0x0ffe, },
{ &ops, W83667HG_A_PECI},
{ &ops, W83667HG_A_VID_BUSSEL},
{ &ops, W83667HG_A_GPIO_PP_OD},

14
src/superio/winbond/w83697hf/superio.c
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@ -77,16 +77,16 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83697HF_MIDI_GPIO5, },
{ &ops, W83697HF_GPIO234, },
{ &ops, W83697HF_ACPI, },
{ &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
{ &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
};
static void enable_dev(struct device *dev)

14
src/superio/winbond/w83977tf/superio.c
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@ -49,13 +49,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, },
{ &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, },
{ &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07f8, },
{ &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, },
{ &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07fe, },
{ &ops, W83977TF_ACPI, PNP_IRQ0, },
};

12
src/superio/winbond/wpcd376i/superio.c
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@ -55,13 +55,13 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, WPCD376I_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, },
{ &ops, WPCD376I_LPT, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, },
{ &ops, WPCD376I_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
{ &ops, WPCD376I_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, WPCD376I_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x07fa, },
{ &ops, WPCD376I_LPT, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x04f8, },
{ &ops, WPCD376I_IR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, 0x07f8, },
{ &ops, WPCD376I_SP1, PNP_IO0 | PNP_IRQ0, 0x07f8, },
{ &ops, WPCD376I_KBCM, PNP_IRQ0, },
{ &ops, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
{ &ops, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, },
{ &ops, WPCD376I_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07f8, 0x07f8, },
{ &ops, WPCD376I_GPIO, PNP_IO0 | PNP_IRQ0, 0xfff8, },
};
static void enable_dev(struct device *dev)