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amd/lx: Move configuration from source to Kconfig 

LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.

These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.

Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)

Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi 2012-07-13 19:06:22 +02:00
parent 1b3207ee61
commit 7dc2864be7
26 changed files with 97 additions and 111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/aaeon/pfm-540i_revb/romstage.c
View File

@ -47,10 +47,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE60EE
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -79,7 +75,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/amd/db800/romstage.c
View File

@ -41,10 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x000005DD /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE60EE
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -74,7 +70,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/amd/norwich/romstage.c
View File

@ -38,10 +38,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

8
src/mainboard/artecgroup/dbe61/romstage.c
View File

@ -51,12 +51,6 @@ static int spd_read_byte(unsigned device, unsigned address)
return 0xFF;
}
#define ManualConf 0 /* Do automatic strapped PLL config */
/* CPU and GLIU mult/div 500/266*/
#define PLLMSRhi 0x0000039C /* 33MHz PCI, 0x000003DD for 66MHz PCI */
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE6000
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -94,7 +88,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/bachmann/ot200/Kconfig
View File

@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select POWER_BUTTON_DEFAULT_DISABLE
select DRIVERS_I2C_IDREG
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@ -25,4 +27,8 @@ config IRQ_SLOT_COUNT
int
default 6
config PLLMSRlo
hex
default 0x07de001e
endif # BOARD_BACHMANN_OT200

6
src/mainboard/bachmann/ot200/romstage.c
View File

@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 1 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x0000039c /* CPU 500 MHz - GLIU 266 MHz */
#define PLLMSRlo 0x07de001e
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/digitallogic/msm800sev/romstage.c
View File

@ -22,10 +22,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -57,7 +53,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/iei/pcisa-lx-800-r10/Kconfig
View File

@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT
int
default 9
config PLLMSRlo
hex
default 0x00DE6000
endif # BOARD_IEI_PCISA_LX_800_R10

10
src/mainboard/iei/pcisa-lx-800-r10/romstage.c
View File

@ -41,14 +41,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 1 /* Do automatic strapped PLL config */
//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/
//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/
#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/
//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0
/* Hold Count - how long we will sit in reset */
#define PLLMSRlo 0x00DE6000
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -78,7 +70,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

19
src/mainboard/iei/pm-lx-800-r11/Kconfig
View File

@ -32,6 +32,8 @@ config BOARD_SPECIFIC_OPTIONS
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_266
config MAINBOARD_DIR
string
@ -45,19 +47,8 @@ config IRQ_SLOT_COUNT
int
default 7
choice
prompt "Core/GLIU Frequency"
default CORE_GLIU_500_266
config CORE_GLIU_500_266
bool "500MHz / 266MHz"
config CORE_GLIU_500_333
bool "500MHz / 333MHz"
config CORE_GLIU_500_400
bool "500MHz / 400MHz"
endchoice
config PLLMSRlo
hex
default 0x07de0000
endif # BOARD_IEI_PM_LX_800_R11

12
src/mainboard/iei/pm-lx-800-r11/romstage.c
View File

@ -46,16 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#if CONFIG_CORE_GLIU_500_400
# define PLLMSRhi 0x0000059c
#elif CONFIG_CORE_GLIU_500_333
# define PLLMSRhi 0x0000049c
#else
# define PLLMSRhi 0x0000039c
#endif
#define PLLMSRlo 0x07de000
#include <northbridge/amd/lx/raminit.h>
#include <northbridge/amd/lx/pll_reset.c>
#include <northbridge/amd/lx/raminit.c>
@ -80,7 +70,7 @@ void main(unsigned long bist)
report_bist_failure(bist);
pll_reset(1);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/lippert/hurricane-lx/Kconfig
View File

@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# Board is equipped with a 1 MB SPI flash, however, due to limitations
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_333
config MAINBOARD_DIR
string
@ -50,4 +52,8 @@ config ONBOARD_UARTS_RS485
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_HURRICANE_LX

6
src/mainboard/lippert/hurricane-lx/romstage.c
View File

@ -40,10 +40,6 @@
/* Bit0 enables Spread Spectrum. */
#define SMC_CONFIG 0x01
#define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
@ -138,7 +134,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/lippert/literunner-lx/Kconfig
View File

@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@ -42,4 +44,8 @@ config ONBOARD_IDE_SLAVE
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_LITERUNNER_LX

6
src/mainboard/lippert/literunner-lx/romstage.c
View File

@ -44,10 +44,6 @@
#define SMC_CONFIG 0x01
#endif
#define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
@ -181,7 +177,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/lippert/roadrunner-lx/Kconfig
View File

@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# SST 49LF008A is possible.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_333
config MAINBOARD_DIR
string
@ -34,4 +36,8 @@ config ONBOARD_UARTS_RS485
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_ROADRUNNER_LX

6
src/mainboard/lippert/roadrunner-lx/romstage.c
View File

@ -37,10 +37,6 @@
#include "southbridge/amd/cs5536/early_setup.c"
#include "superio/ite/it8712f/early_serial.c"
#define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000049C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
@ -113,7 +109,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/lippert/spacerunner-lx/Kconfig
View File

@ -15,6 +15,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# of the IT8712F Super I/O, only the top 512 KB are directly mapped.
select BOARD_ROMSIZE_KB_512
select POWER_BUTTON_FORCE_ENABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@ -41,4 +43,8 @@ config ONBOARD_IDE_SLAVE
help
If selected, the on-board SSD will act as IDE Slave instead of Master.
config PLLMSRlo
hex
default 0x00de6001
endif # BOARD_LIPPERT_SPACERUNNER_LX

6
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@ -44,10 +44,6 @@
#define SMC_CONFIG 0x01
#endif
#define ManualConf 1 /* No automatic strapped PLL config */
#define PLLMSRhi 0x0000059C /* Manual settings for the PLL */
#define PLLMSRlo 0x00DE6001
static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I
0xFF, 0xFF, // only values used by Geode-LX raminit.c are set
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, // (Fundamental) memory type
@ -178,7 +174,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/pcengines/alix1c/romstage.c
View File

@ -99,10 +99,6 @@ static u8 spd_read_byte(u8 device, u8 address)
return spdbytes[address];
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
#define PLLMSRlo 0x02000030
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -132,7 +128,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/pcengines/alix2d/romstage.c
View File

@ -98,10 +98,6 @@ static u8 spd_read_byte(u8 device, u8 address)
return spdbytes[address];
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
#define PLLMSRlo 0x02000030
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -156,7 +152,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/traverse/geos/Kconfig
View File

@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select UDELAY_TSC
select BOARD_ROMSIZE_KB_1024
select POWER_BUTTON_DEFAULT_DISABLE
select PLL_MANUAL_CONFIG
select CORE_GLIU_500_400
config MAINBOARD_DIR
string
@ -24,4 +26,8 @@ config IRQ_SLOT_COUNT
int
default 6
config PLLMSRlo
hex
default 0x00de602e
endif # BOARD_TRAVERSE_GEOS

6
src/mainboard/traverse/geos/romstage.c
View File

@ -39,10 +39,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 1 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x0000059C /* manual settings for the PLL */
#define PLLMSRlo 0x00DE602E
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -75,7 +71,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

6
src/mainboard/winent/pl6064/romstage.c
View File

@ -43,10 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
#define PLLMSRlo 0x02000030
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@ -77,7 +73,7 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset(ManualConf);
pll_reset();
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);

31
src/northbridge/amd/lx/Kconfig
View File

@ -2,7 +2,36 @@ config NORTHBRIDGE_AMD_LX
bool
select GEODE_VSA
if NORTHBRIDGE_AMD_LX
config VIDEO_MB
int
default 8
depends on NORTHBRIDGE_AMD_LX
config PLL_MANUAL_CONFIG
bool
if PLL_MANUAL_CONFIG
# "Core/GLIU Frequency"
config CORE_GLIU_500_266
bool # "500MHz / 266MHz"
config CORE_GLIU_500_333
bool # "500MHz / 333MHz"
config CORE_GLIU_500_400
bool # "500MHz / 400MHz"
config PLLMSRhi
hex
default 0x39c if CORE_GLIU_500_266
default 0x49c if CORE_GLIU_500_333
default 0x59c if CORE_GLIU_500_400
config PLLMSRlo
hex
endif
endif

8
src/northbridge/amd/lx/pll_reset.c
View File

@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
static void pll_reset(char manualconf)
static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
@ -31,13 +31,13 @@ static void pll_reset(char manualconf)
if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
printk(BIOS_DEBUG, "Configuring PLL.\n");
if (manualconf) {
if (CONFIG_PLL_MANUAL_CONFIG) {
post_code(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
msrGlcpSysRstpll.hi = PLLMSRhi;
msrGlcpSysRstpll.hi = CONFIG_PLLMSRhi;
/* Hold Count - how long we will sit in reset */
msrGlcpSysRstpll.lo = PLLMSRlo;
msrGlcpSysRstpll.lo = CONFIG_PLLMSRlo;
} else {
/*automatic configuration (straps) */
post_code(POST_PLL_STRAP);