snow: Add flush to UART driver.
Wait for UART FIFO to be ready. (Credit to dhendrix for finding the bits to test with.) Change-Id: Ib6733e422cbc1c61b942bd90d85f88a3f412d6ff Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3698 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -162,12 +162,19 @@ static void exynos5_uart_tx_byte(unsigned char data)
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writeb(data, &uart->utxh);
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}
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static void exynos5_uart_tx_flush(void)
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{
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struct s5p_uart *uart = (struct s5p_uart *)base_port;
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while (readl(&uart->ufstat) & 0x1ff0000);
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}
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#if !defined(__PRE_RAM__)
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static const struct console_driver exynos5_uart_console __console = {
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.init = exynos5_init_dev,
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.tx_byte = exynos5_uart_tx_byte,
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// .tx_flush = exynos5_uart_tx_flush,
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.tx_flush = exynos5_uart_tx_flush,
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.rx_byte = exynos5_uart_rx_byte,
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// .tst_byte = exynos5_uart_tst_byte,
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};
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@ -196,6 +203,7 @@ void uart_tx_byte(unsigned char data)
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void uart_tx_flush(void)
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{
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exynos5_uart_tx_flush();
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}
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#endif
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