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soc/mediatek/mt8192: Reserve 44K SRAM for MCUPM working buffer 

Reduce PRERAM_CBMEM_CONSOLE buffer from 63K to 19K and reserve
0x00115000 ~ 0x0011ffff for MCUPM.

Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ic82a194736eecd7bdc8df80b493290090a2ccba5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Yidi Lin 2020-11-11 10:44:15 +08:00 committed by Patrick Georgi
parent 93538c9969
commit 7de8df467a
1 changed files with 10 additions and 5 deletions
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15
src/soc/mediatek/mt8192/include/soc/memlayout.ld
View File

@ -21,11 +21,16 @@ SECTIONS
TPM_TCPA_LOG(0x00103000, 2K) TPM_TCPA_LOG(0x00103000, 2K)
FMAP_CACHE(0x00103800, 2K) FMAP_CACHE(0x00103800, 2K)
WATCHDOG_TOMBSTONE(0x00104000, 4) WATCHDOG_TOMBSTONE(0x00104000, 4)
PRERAM_CBMEM_CONSOLE(0x00104004, 63K - 4) PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4)
TIMESTAMP(0x00113c00, 1K) TIMESTAMP(0x00108c00, 1K)
STACK(0x00114000, 16K) STACK(0x00109000, 16K)
TTB(0x00118000, 28K) TTB(0x0010d000, 28K)
DMA_COHERENT(0x0011f000, 4K) DMA_COHERENT(0x00114000, 4K)
/*
* MCUPM exchanges data with kernel driver using SRAM 0x00115000 ~ 0x0011ffff.
* The address is hardcoded in MCUPM image and is unlikely to change.
*/
REGION(mcufw_reserved, 0x00115000, 44K, 4K)
SRAM_END(0x00120000) SRAM_END(0x00120000)
SRAM_L2C_START(0x00200000) SRAM_L2C_START(0x00200000)