mb/lenovo/x201: Link gpio map instead of including a header

Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.

Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

src/mainboard/lenovo/x201/Makefile.inc

@@ -17,3 +17,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 romstage-y += dock.c
 ramstage-y += dock.c
+romstage-y += gpio.c

src/mainboard/lenovo/x201/gpio.c

@@ -378,7 +378,7 @@ const struct pch_gpio_set3 pch_gpio_set3_level = {
 	.gpio75 = GPIO_LEVEL_LOW,
 };
 
-const struct pch_gpio_map x201_gpio_map = {
+const struct pch_gpio_map mainboard_gpio_map = {
 	.set1 = {
 		.mode      = &pch_gpio_set1_mode,
 		.direction = &pch_gpio_set1_direction,

src/mainboard/lenovo/x201/romstage.c

@@ -37,10 +37,10 @@
 #include <cbmem.h>
 #include <tpm.h>
 
-#include "gpio.h"
 #include "dock.h"
 #include "arch/early_variables.h"
 #include <southbridge/intel/ibexpeak/pch.h>
+#include <southbridge/intel/common/gpio.h>
 #include <northbridge/intel/nehalem/nehalem.h>
 
 #include <northbridge/intel/nehalem/raminit.h>
@@ -200,7 +200,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 
-	setup_pch_gpios(&x201_gpio_map);
+	setup_pch_gpios(&mainboard_gpio_map);
 
 
 	/* This should probably go away. Until now it is required