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Here is a proposed way how to handle the SATA PHY settings on SB700. It 

consits of weak function which always exists (with defaults) and a possibility to 
 override this with normal function in main.c. This is the other way of 
 doing that and not using the devictree.cb.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek 2010-09-22 22:46:47 +00:00
parent 138cdbb17b
commit 7df50a8b0e
3 changed files with 51 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/mainboard/asrock/939a785gmh/mainboard.c
View File

@ -147,3 +147,25 @@ struct chip_operations mainboard_ops = {
CHIP_NAME("Asrock 939A785GMH/128M Mainboard")
.enable_dev = mb_enable,
};
/* override the default SATA PHY setup */
void sb700_setup_sata_phys(struct device *dev) {
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
pci_write_config16(dev, 0x86, 0x2c00);
/* RPR7.6.2 SATA GENI PHY ports setting */
pci_write_config32(dev, 0x88, 0x01B48016);
pci_write_config32(dev, 0x8c, 0x01B48016);
pci_write_config32(dev, 0x90, 0x01B48016);
pci_write_config32(dev, 0x94, 0x01B48016);
pci_write_config32(dev, 0x98, 0x01B48016);
pci_write_config32(dev, 0x9C, 0x01B48016);
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
pci_write_config16(dev, 0xA0, 0xA07A);
pci_write_config16(dev, 0xA2, 0xA07A);
pci_write_config16(dev, 0xA4, 0xA07A);
pci_write_config16(dev, 0xA6, 0xA07A);
pci_write_config16(dev, 0xA8, 0xA07A);
pci_write_config16(dev, 0xAA, 0xA0FF);
}

5
src/southbridge/amd/sb700/sb700.h
View File

@ -52,6 +52,11 @@ void sb700_enable(device_t dev);
#ifdef __PRE_RAM__
void sb700_lpc_port80(void);
void sb700_pci_port80(void);
#else
#include <device/pci.h>
/* allow override in mainboard.c */
void sb700_setup_sata_phys(struct device *dev);
#endif
#endif /* SB700_H */

45
src/southbridge/amd/sb700/sb700_sata.c
View File

@ -53,6 +53,29 @@ static int sata_drive_detect(int portnum, u16 iobar)
return 0;
}
/* This function can be overloaded in mainboard.c */
void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) {
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
pci_write_config16(dev, 0x86, 0x2c00);
/* RPR7.6.2 SATA GENI PHY ports setting */
pci_write_config32(dev, 0x88, 0x01B48017);
pci_write_config32(dev, 0x8c, 0x01B48019);
pci_write_config32(dev, 0x90, 0x01B48016);
pci_write_config32(dev, 0x94, 0x01B48016);
pci_write_config32(dev, 0x98, 0x01B48016);
pci_write_config32(dev, 0x9C, 0x01B48016);
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
pci_write_config16(dev, 0xA0, 0xA09A);
pci_write_config16(dev, 0xA2, 0xA09F);
pci_write_config16(dev, 0xA4, 0xA07A);
pci_write_config16(dev, 0xA6, 0xA07A);
pci_write_config16(dev, 0xA8, 0xA07A);
pci_write_config16(dev, 0xAA, 0xA07A);
}
static void sata_init(struct device *dev)
{
u8 byte;
@ -161,27 +184,7 @@ static void sata_init(struct device *dev)
/* Program the watchdog counter to 0x10 */
byte = 0x10;
pci_write_config8(dev, 0x46, byte);
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
word = 0x2c00;
pci_write_config16(dev, 0x86, word);
/* RPR7.6.2 SATA GENI PHY ports setting */
pci_write_config32(dev, 0x88, 0x01B48017);
pci_write_config32(dev, 0x8c, 0x01B48019);
pci_write_config32(dev, 0x90, 0x01B48016);
pci_write_config32(dev, 0x94, 0x01B48016);
pci_write_config32(dev, 0x98, 0x01B48016);
pci_write_config32(dev, 0x9C, 0x01B48016);
/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
pci_write_config16(dev, 0xA0, 0xA09A);
pci_write_config16(dev, 0xA2, 0xA09F);
pci_write_config16(dev, 0xA4, 0xA07A);
pci_write_config16(dev, 0xA6, 0xA07A);
pci_write_config16(dev, 0xA8, 0xA07A);
pci_write_config16(dev, 0xAA, 0xA07A);
sb700_setup_sata_phys(dev);
/* Enable the I/O, MM, BusMaster access for SATA */
byte = pci_read_config8(dev, 0x4);
byte |= 7 << 0;