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soc/intel/meteorlake: Move ME firmware status register structures to 

pertinent header file

This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.

The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.

The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarilly share the same SoC directory.

BUG=b:260309647
Test=Able to build and boot Google/rex

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Dinesh Gehlot 2023-01-03 04:13:31 +00:00 committed by Felix Held
parent bd8112ae2b
commit 7df8a69b26
2 changed files with 64 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
src/soc/intel/meteorlake/include/soc/me.h
View File

@ -3,43 +3,79 @@
#ifndef _METEORLAKE_ME_H_
#define _METEORLAKE_ME_H_
#include <stdint.h>
/* ME Host Firmware Status register 1 */
union me_hfsts1 {
u32 data;
uint32_t data;
struct {
u32 working_state: 4;
u32 mfg_mode: 1;
u32 fpt_bad: 1;
u32 operation_state: 3;
u32 fw_init_complete: 1;
u32 ft_bup_ld_flr: 1;
u32 update_in_progress: 1;
u32 error_code: 4;
u32 operation_mode: 4;
u32 reset_count: 4;
u32 boot_options_present: 1;
u32 invoke_enhance_dbg_mode: 1;
u32 bist_test_state: 1;
u32 bist_reset_request: 1;
u32 current_power_source: 2;
u32 reserved: 1;
u32 d0i3_support_valid: 1;
uint32_t working_state : 4;
uint32_t mfg_mode : 1;
uint32_t fpt_bad : 1;
uint32_t operation_state : 3;
uint32_t fw_init_complete : 1;
uint32_t ft_bup_ld_flr : 1;
uint32_t update_in_progress : 1;
uint32_t error_code : 4;
uint32_t operation_mode : 4;
uint32_t reserved_0 : 4;
uint32_t boot_options_present : 1;
uint32_t invoke_enhance_dbg_mode: 1;
uint32_t reserved_1 : 5;
uint32_t d0i3_support_valid : 1;
} __packed fields;
};
/* Host Firmware Status Register 2 */
union me_hfsts2 {
uint32_t data;
struct {
uint32_t reserved_0 : 4;
uint32_t cpu_replaced : 1;
uint32_t reserved_1 : 3;
uint32_t cpu_replaced_valid : 1;
uint32_t low_power_state : 1;
uint32_t reserved_2 : 22;
} __packed fields;
};
/* ME Host Firmware Status Register 3 */
union me_hfsts3 {
u32 data;
uint32_t data;
struct {
u32 reserved_0: 4;
u32 fw_sku: 3;
u32 reserved_7: 2;
u32 reserved_9: 2;
u32 resered_11: 3;
u32 resered_14: 16;
u32 reserved_30: 2;
uint32_t reserved_0 : 4;
uint32_t fw_sku : 3;
uint32_t reserved_1 : 25;
} __packed fields;
};
/* Host Firmware Status Register 4 */
union me_hfsts4 {
uint32_t data;
struct {
uint32_t rsvd0;
} __packed fields;
};
/* Host Firmware Status Register 5 */
union me_hfsts5 {
uint32_t data;
struct {
uint32_t reserved_0 : 17;
uint32_t txt_support : 1;
uint32_t reserved_1 : 3;
uint32_t cpu_debug_disabled : 1;
uint32_t reserved_2 : 10;
} __packed fields;
};
/* Host Firmware Status Register 6 */
union me_hfsts6 {
uint32_t data;
struct {
uint32_t reserved_0 : 21;
uint32_t manuf_lock : 1;
uint32_t reserved_1 : 8;
uint32_t fpf_soc_lock : 1;
uint32_t reserved_2 : 1;
} __packed fields;
};
#endif

70
src/soc/intel/meteorlake/me.c
View File

@ -6,76 +6,6 @@
#include <soc/me.h>
#include <stdint.h>
/* Host Firmware Status Register 2 */
union me_hfsts2 {
uint32_t data;
struct {
uint32_t nftp_load_failure : 1;
uint32_t icc_prog_status : 2;
uint32_t invoke_mebx : 1;
uint32_t cpu_replaced : 1;
uint32_t rsvd0 : 1;
uint32_t mfs_failure : 1;
uint32_t warm_reset_rqst : 1;
uint32_t cpu_replaced_valid : 1;
uint32_t low_power_state : 1;
uint32_t me_power_gate : 1;
uint32_t ipu_needed : 1;
uint32_t forced_safe_boot : 1;
uint32_t rsvd1 : 2;
uint32_t listener_change : 1;
uint32_t status_data : 8;
uint32_t current_pmevent : 4;
uint32_t phase : 4;
} __packed fields;
};
/* Host Firmware Status Register 4 */
union me_hfsts4 {
uint32_t data;
struct {
uint32_t rsvd0 : 1;
uint32_t flash_log_exist : 1;
uint32_t rsvd1 : 30;
} __packed fields;
};
/* Host Firmware Status Register 5 */
union me_hfsts5 {
uint32_t data;
struct {
uint32_t acm_active : 1;
uint32_t valid : 1;
uint32_t result_code_source : 1;
uint32_t error_status_code : 5;
uint32_t acm_done_sts : 1;
uint32_t timeout_count : 7;
uint32_t scrtm_indicator : 1;
uint32_t txt_support : 1;
uint32_t btg_profile : 3;
uint32_t cpu_debug_disabled : 1;
uint32_t bsp_init_disabled : 1;
/* BSP Boot Policy Manifest Execution Status */
uint32_t bsp_bpm_exe_sts : 1;
uint32_t btg_token_applied : 1;
uint32_t btg_status : 4;
uint32_t rsvd0 : 2;
uint32_t start_enforcement : 1;
} __packed fields;
};
/* Host Firmware Status Register 6 */
union me_hfsts6 {
uint32_t data;
struct {
uint32_t rsvd0 : 21;
uint32_t manuf_lock : 1;
uint32_t rsvd2 : 8;
uint32_t fpf_soc_lock : 1;
uint32_t sx_resume_type : 1;
} __packed fields;
};
static bool is_manufacturing_mode(union me_hfsts1 hfsts1, union me_hfsts6 hfsts6)
{
/*