i945/gma.c: use linux code to calculate divisors
The code to compute n, m1, m2, p1 divisors is not correct in coreboot and on some targets hits a working mode at lower refresh rate, which is why display is working on some targets. The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2) / (p1 * p2)" is as close as possible to the target frequency (which is defined by the resolution and refresh rate). This patch also fixes the reference frequency. This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c to correctly compute divisors. The result is that some previously not working displays, like many displays found on the Lenovo T60 might work now. Some examples of T60 displays that were known to not work (in payload): Samsung LTN141XA-L01 (14.1" 1024x768) LG-Philips LP150X09 (15.1" 1024x768) IDtech N150U3-L01 (15.1" 1600x1200) IDtech IAQX10N (15.1" 2048x1536) Samsung LTN154X3-L0A (15.4" 1280x800) LG-Philips LP150E06-A5K4 (15.1" 1400x1050) Tested on T60 with 1024x786. Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16504 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
494d398ae4
commit
7dfc8a5ebd
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@ -26,6 +26,7 @@
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#include <string.h>
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#include <commonlib/helpers.h>
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#include "i945.h"
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#include "chip.h"
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@ -43,7 +44,7 @@
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#define PGETBL_CTL 0x2020
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#define PGETBL_ENABLED 0x00000001
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#define BASE_FREQUENCY 120000
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#define BASE_FREQUENCY 100000
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#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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@ -85,10 +86,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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u8 edid_data[128];
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unsigned long temp;
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int hpolarity, vpolarity;
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u32 candp1, candn;
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u32 best_delta = 0xffffffff;
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u32 smallest_err = 0xffffffff;
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u32 target_frequency;
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u32 pixel_p1 = 1;
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u32 pixel_p2;
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u32 pixel_n = 1;
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u32 pixel_m1 = 1;
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u32 pixel_m2 = 1;
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@ -158,43 +159,39 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
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write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
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target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
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: (2 * mode->pixel_clock);
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/* p2 divisor must 7 for dual channel LVDS */
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/* and 14 for single channel LVDS */
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pixel_p2 = mode->lvds_dual_channel ? 7 : 14;
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target_frequency = mode->pixel_clock;
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/* Find suitable divisors. */
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for (candp1 = 1; candp1 <= 8; candp1++) {
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for (candn = 5; candn <= 10; candn++) {
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u32 cur_frequency;
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u32 m; /* 77 - 131. */
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u32 denom; /* 35 - 560. */
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u32 current_delta;
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denom = candn * candp1 * 7;
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/* Doesnt overflow for up to
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5000000 kHz = 5 GHz. */
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m = (target_frequency * denom
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+ BASE_FREQUENCY / 2) / BASE_FREQUENCY;
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if (m < 77 || m > 131)
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continue;
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cur_frequency = (BASE_FREQUENCY * m) / denom;
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if (target_frequency > cur_frequency)
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current_delta = target_frequency - cur_frequency;
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else
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current_delta = cur_frequency - target_frequency;
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if (best_delta > current_delta) {
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best_delta = current_delta;
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pixel_n = candn;
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pixel_p1 = candp1;
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pixel_m2 = ((m + 3) % 5) + 7;
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pixel_m1 = (m - pixel_m2) / 5;
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/* Find suitable divisors, m1, m2, p1, n. */
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/* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */
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/* should be closest to target frequency as possible */
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u32 candn, candm1, candm2, candp1;
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for (candm1 = 8; candm1 <= 18; candm1++) {
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for (candm2 = 3; candm2 <= 7; candm2++) {
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for (candn = 1; candn <= 6; candn++) {
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for (candp1 = 1; candp1 <= 8; candp1++) {
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u32 m = 5 * (candm1 + 2) + (candm2 + 2);
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u32 p = candp1 * pixel_p2;
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u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);
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u32 dot = DIV_ROUND_CLOSEST(vco, p);
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u32 this_err = ABS(dot - target_frequency);
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if ((m < 70) || (m > 120))
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continue;
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if (this_err < smallest_err) {
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smallest_err = this_err;
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pixel_n = candn;
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pixel_m1 = candm1;
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pixel_m2 = candm2;
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pixel_p1 = candp1;
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}
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}
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}
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}
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}
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if (best_delta == 0xffffffff) {
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if (smallest_err == 0xffffffff) {
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printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
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return -1;
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}
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@ -216,8 +213,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
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pixel_n, pixel_m1, pixel_m2, pixel_p1);
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printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
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BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
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/ (pixel_p1 * 7));
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BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
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(pixel_n + 2) / (pixel_p1 * pixel_p2));
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#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
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@ -242,8 +239,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
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| (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
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write32(pmmio + FP0(1),
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((pixel_n - 2) << 16)
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| ((pixel_m1 - 2) << 8) | pixel_m2);
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(pixel_n << 16)
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| (pixel_m1 << 8) | pixel_m2);
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write32(pmmio + DPLL(1),
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DPLL_VGA_MODE_DIS |
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DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
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@ -252,8 +249,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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| (conf->gpu_lvds_use_spread_spectrum_clock
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? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
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: 0)
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| (pixel_p1 << 16)
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| (pixel_p1));
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| (0x10000 << (pixel_p1 - 1)));
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mdelay(1);
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write32(pmmio + DPLL(1),
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DPLL_VGA_MODE_DIS |
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@ -261,8 +257,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
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| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
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: DPLLB_LVDS_P2_CLOCK_DIV_14)
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| ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
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| (pixel_p1 << 16)
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| (pixel_p1));
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| (0x10000 << (pixel_p1 - 1)));
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mdelay(1);
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write32(pmmio + HTOTAL(1),
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((hactive + right_border + hblank - 1) << 16)
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