diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index 84206823a9..679e022f64 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -18,6 +18,7 @@
Start Booting
Early Debug
Bootblock
+ TempRamInit
@@ -195,6 +196,94 @@ mv build/coreboot.rom.new build/coreboot.rom
+
+
+
+ Enable the call to TempRamInit in two stages:
+
+
+ - Finding the FSP binary in the read-only CBFS region
+ - Call TempRamInit
+
+
+
+Find FSP Binary
+
+Use the following steps to locate the FSP binary:
+
+
+ - Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
+
+ - Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
+ src/drivers/intel/fsp1_1/cache_as_ram.inc
+
+ - Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
+ specifically building
+ util.c
+
+
+
+ - Debug the result until port 0x80 outputs
+
+ - 0x90: POST_FSP_TEMP_RAM_INIT
+ - Just before calling
+ TempRamInit
+
+ - Alternating 0xba and 0x01 - The FSP image was not found
+
+
+ - Add the FSP binary file to the flash image
+ - Set the following Kconfig values:
+
+ - CONFIG_FSP_LOC to the FSP base address specified in the previous step
+ - CONFIG_FSP_IMAGE_ID_STRING
+
+
+ - Debug the result until port 0x80 outputs
+
+ - 0x90: POST_FSP_TEMP_RAM_INIT
+ - Just before calling
+ TempRamInit
+
+ - Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found
+
+
+
+
+
+Calling TempRamInit
+
+Use the following steps to debug the call to TempRamInit:
+
+
+ - Add the CPU microcode update file
+
+ - Add the microcode file with the following command
+
util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin
+
+ - Set the Kconfig values
+
+ - CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step
+ - CONFIG_CPU_MICROCODE_CBFS_LEN
+
+
+
+
+ - Debug the result until port 0x80 outputs
+
+ - 0x90: POST_FSP_TEMP_RAM_INIT
+ - Just before calling
+ TempRamInit
+
+ - 0x2A - Just before calling
+ cache_as_ram_main
+ which is the start of the verstage code which may be part of romstage
+
+
+
+
+
+
Modified: 31 January 2016