mainboards/apollolake: Set RAPL power limit PL1 value to 12W.
This patch sets tuned RAPL power limit PL1 value to 12W in acpi/dptf.asl for RAPL MSR register. With PL1 as 12W for WebGL and stream case, we measured SoC power reaching upto 6W. Above 12W PL1 value, we observed that Soc power going above 6W. With PL1 as 12W, system is able to leverage full TDP capacity. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -73,7 +73,7 @@ Name (MPPC, Package ()
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Package () { /* Power Limit 1 */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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1600, /* PowerLimitMinimum */
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1600, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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12000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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200 /* StepSize */
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@ -73,7 +73,7 @@ Name (MPPC, Package ()
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Package () { /* Power Limit 1 */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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1600, /* PowerLimitMinimum */
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1600, /* PowerLimitMinimum */
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15000, /* PowerLimitMaximum */
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12000, /* PowerLimitMaximum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMinimum */
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1000, /* TimeWindowMaximum */
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1000, /* TimeWindowMaximum */
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200 /* StepSize */
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200 /* StepSize */
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