siemens/mc_apl1: Make the DDR memory swizzle data configurable
In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer
Werner Zeh
parent
899e2ce6ce
commit
7e15e87ecc
|
|
@ -18,39 +18,17 @@
|
|||
#include <hwilib.h>
|
||||
#include <lib.h>
|
||||
#include <string.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <fsp/api.h>
|
||||
#include <FspmUpd.h>
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
static const uint8_t Ch0_Bit_swizzling[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
static const uint8_t Ch1_Bit_swizzling[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
static const uint8_t Ch2_Bit_swizzling[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
static const uint8_t Ch3_Bit_swizzling[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd)
|
||||
{
|
||||
const struct pad_config *pads;
|
||||
const struct lpddr4_swizzle_cfg *cfg;
|
||||
const struct lpddr4_chan_swizzle_cfg *chan;
|
||||
uint8_t spd[0x80];
|
||||
size_t num;
|
||||
|
||||
|
|
@ -58,7 +36,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
|
|||
pads = variant_early_gpio_table(&num);
|
||||
gpio_configure_pads(pads, num);
|
||||
|
||||
/* Get DRAM configuration data from hwinfo block.
|
||||
/*
|
||||
* Get DRAM configuration data from hwinfo block.
|
||||
* The configuration data from hwinfo block is a one-to-one
|
||||
* representation of the FSPM_UPD data starting with parameter
|
||||
* 'Package' (offset 0x4d) and ending before parameter
|
||||
|
|
@ -80,14 +59,70 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
|
|||
(((uint8_t *)memupd->FspmConfig.Ch0_Bit_swizzling)-
|
||||
(&memupd->FspmConfig.Package)));
|
||||
|
||||
memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
|
||||
sizeof(Ch0_Bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
|
||||
sizeof(Ch1_Bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
|
||||
sizeof(Ch2_Bit_swizzling));
|
||||
memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
|
||||
sizeof(Ch3_Bit_swizzling));
|
||||
/*
|
||||
* Some of the mc_apl1 boards use LPDDR4 memory. In this case, the
|
||||
* correct swizzle configuration is necessary. The default settings
|
||||
* for swizzling are 0, since the baseboard does not use LPDDR4 memory.
|
||||
*/
|
||||
cfg = variant_lpddr4_swizzle_config();
|
||||
|
||||
/*
|
||||
* CH0_DQB byte lanes in the bit swizzle configuration field are
|
||||
* not 1:1. The mapping within the swizzling field is:
|
||||
* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
|
||||
* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
|
||||
* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
|
||||
* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
|
||||
*/
|
||||
chan = &cfg->phys[LP4_PHYS_CH0B];
|
||||
memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[0], &chan->dqs[LP4_DQS1],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[8], &chan->dqs[LP4_DQS0],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[16], &chan->dqs[LP4_DQS3],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch0_Bit_swizzling[24], &chan->dqs[LP4_DQS2],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
|
||||
/* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1. */
|
||||
chan = &cfg->phys[LP4_PHYS_CH0A];
|
||||
memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[0], &chan->dqs[LP4_DQS0],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[8], &chan->dqs[LP4_DQS1],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[16], &chan->dqs[LP4_DQS2],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
|
||||
/*
|
||||
* CH1_DQB byte lanes in the bit swizzle configuration field are
|
||||
* not 1:1. The mapping within the swizzling field is:
|
||||
* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
|
||||
* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
|
||||
* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
|
||||
* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
|
||||
*/
|
||||
chan = &cfg->phys[LP4_PHYS_CH1B];
|
||||
memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[0], &chan->dqs[LP4_DQS1],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[8], &chan->dqs[LP4_DQS0],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[16], &chan->dqs[LP4_DQS3],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch2_Bit_swizzling[24], &chan->dqs[LP4_DQS2],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
|
||||
/* CH1_DQA byte lanes in the bit swizzle configuration field are 1:1. */
|
||||
chan = &cfg->phys[LP4_PHYS_CH1A];
|
||||
memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[0], &chan->dqs[LP4_DQS0],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[8], &chan->dqs[LP4_DQS1],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[16], &chan->dqs[LP4_DQS2],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
memcpy(&memupd->FspmConfig.Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3],
|
||||
(size_t)DQ_BITS_PER_DQS);
|
||||
|
||||
memupd->FspmConfig.MsgLevelMask = 0x0;
|
||||
memupd->FspmConfig.MrcDataSaving = 0x0;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
romstage-y += gpio.c
|
||||
romstage-y += memory.c
|
||||
|
||||
ramstage-y += gpio.c
|
||||
|
|
|
|||
|
|
@ -26,6 +26,9 @@
|
|||
const struct pad_config *variant_gpio_table(size_t *num);
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num);
|
||||
|
||||
/* This function provides the swizzle data for the DRAM initialization. */
|
||||
const struct lpddr4_swizzle_cfg *variant_lpddr4_swizzle_config(void);
|
||||
|
||||
/* The following function performs board specific things. */
|
||||
void variant_mainboard_final(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright 2016 Google Inc.
|
||||
* Copyright (C) 2018 Siemens AG
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <compiler.h>
|
||||
#include <soc/meminit.h>
|
||||
|
||||
const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
|
||||
/* CH0_DQA[0:31] SoC pins -> U22 LPDDR4 module pins */
|
||||
.phys[LP4_PHYS_CH0A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH0B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1A] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
},
|
||||
.phys[LP4_PHYS_CH1B] = {
|
||||
/* DQA[0:7] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS0] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQA[8:15] pins of LPDDR4 module. */
|
||||
.dqs[LP4_DQS1] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[0:7] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS2] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
/* DQB[7:15] pins of LPDDR4 module with offset of 16. */
|
||||
.dqs[LP4_DQS3] = { 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
},
|
||||
};
|
||||
|
||||
const struct lpddr4_swizzle_cfg * __weak variant_lpddr4_swizzle_config(void)
|
||||
{
|
||||
return &baseboard_lpddr4_swizzle;
|
||||
}
|
||||
Loading…
Reference in New Issue