cpu/amd: Always fetch CPU addr bits at runtime
All supported AMD CPUs support getting the physical address size from cpuid so there is no need for a Kconfig default value. Change-Id: If6f9234e091f44a2a03012e7e14c380aefbe717e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -4,6 +4,7 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <arch/cpu.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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@ -85,7 +86,6 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
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void amd_setup_mtrrs(void)
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{
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unsigned long address_bits;
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unsigned long i;
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msr_t msr, sys_cfg;
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// Test if this CPU is a Fam 0Fh rev. F or later
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@ -142,13 +142,6 @@ void amd_setup_mtrrs(void)
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enable_cache();
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//K8 could be 40, and GH could be 48
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address_bits = CONFIG_CPU_ADDR_BITS;
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/* AMD specific cpuid function to query number of address bits */
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if (cpuid_eax(0x80000000) >= 0x80000008)
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address_bits = cpuid_eax(0x80000008) & 0xff;
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/* Now that I have mapped what is memory and what is not
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* Set up the mtrrs so we can cache the memory.
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*/
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@ -156,5 +149,5 @@ void amd_setup_mtrrs(void)
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// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need
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// variable MTRR to span memory above 4GB
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// Lower revisions K8 need variable MTRR over 4GB
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x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
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x86_setup_var_mtrrs(cpu_phys_address_size(), has_tom2wb ? 0 : 1);
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}
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