From 7e28c846c3dfea730202d858682bec4dc46de1d7 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Sat, 24 Apr 2021 21:22:10 +0800 Subject: [PATCH] mb/hp: Add EliteBook 820 G2 Most of the components of this laptop are tested to work, which is listed in the documentation. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630 Reviewed-by: Martin L Roth Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- .../mainboard/hp/elitebook_820_g2.md | 141 ++++++++++++++++++ .../mainboard/hp/elitebook_820_g2_flash.jpg | Bin 0 -> 86225 bytes Documentation/mainboard/index.md | 1 + src/mainboard/hp/elitebook_820_g2/Kconfig | 31 ++++ .../hp/elitebook_820_g2/Kconfig.name | 4 + .../hp/elitebook_820_g2/Makefile.inc | 6 + src/mainboard/hp/elitebook_820_g2/acpi/ec.asl | 3 + .../hp/elitebook_820_g2/acpi/platform.asl | 14 ++ .../hp/elitebook_820_g2/acpi/superio.asl | 3 + .../hp/elitebook_820_g2/board_info.txt | 7 + src/mainboard/hp/elitebook_820_g2/data.vbt | Bin 0 -> 4493 bytes .../hp/elitebook_820_g2/devicetree.cb | 89 +++++++++++ src/mainboard/hp/elitebook_820_g2/dsdt.asl | 31 ++++ .../hp/elitebook_820_g2/gma-mainboard.ads | 18 +++ src/mainboard/hp/elitebook_820_g2/gpio.c | 110 ++++++++++++++ src/mainboard/hp/elitebook_820_g2/hda_verb.c | 72 +++++++++ src/mainboard/hp/elitebook_820_g2/pei_data.c | 41 +++++ 17 files changed, 571 insertions(+) create mode 100644 Documentation/mainboard/hp/elitebook_820_g2.md create mode 100644 Documentation/mainboard/hp/elitebook_820_g2_flash.jpg create mode 100644 src/mainboard/hp/elitebook_820_g2/Kconfig create mode 100644 src/mainboard/hp/elitebook_820_g2/Kconfig.name create mode 100644 src/mainboard/hp/elitebook_820_g2/Makefile.inc create mode 100644 src/mainboard/hp/elitebook_820_g2/acpi/ec.asl create mode 100644 src/mainboard/hp/elitebook_820_g2/acpi/platform.asl create mode 100644 src/mainboard/hp/elitebook_820_g2/acpi/superio.asl create mode 100644 src/mainboard/hp/elitebook_820_g2/board_info.txt create mode 100644 src/mainboard/hp/elitebook_820_g2/data.vbt create mode 100644 src/mainboard/hp/elitebook_820_g2/devicetree.cb create mode 100644 src/mainboard/hp/elitebook_820_g2/dsdt.asl create mode 100644 src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads create mode 100644 src/mainboard/hp/elitebook_820_g2/gpio.c create mode 100644 src/mainboard/hp/elitebook_820_g2/hda_verb.c create mode 100644 src/mainboard/hp/elitebook_820_g2/pei_data.c diff --git a/Documentation/mainboard/hp/elitebook_820_g2.md b/Documentation/mainboard/hp/elitebook_820_g2.md new file mode 100644 index 0000000000..5d35c30211 --- /dev/null +++ b/Documentation/mainboard/hp/elitebook_820_g2.md @@ -0,0 +1,141 @@ +# HP EliteBook 820 G2 + +This page is about the notebook [HP EliteBook 820 G2]. + +## Release status + +HP EliteBook 820 G2 was released in 2015 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. Broadwell mrc.bin and refcode.elf + +HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller. +The EC firmware is stored in the flash chip, but we don't need to touch it +or use it in the coreboot build process. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Broadwell memory reference code binary and reference code blob is needed +when building coreboot. Read the document [Blobs used in Intel Broadwell boards] +on how to get these blobs. + +## Programming + +Before flashing, remove the battery and the hard drive cover according to the +[Maintenance and Service Guide] of this laptop. + +HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB +private flash. To install coreboot, we need to program both flash chips. +Read [HP Sure Start] for detailed information. + +![HP EliteBook 820 G2 flash chip](elitebook_820_g2_flash.jpg) + +To access the system flash, we need to connect the AC adapter to the machine, +then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer] +made with an STM32 development board is tested to work. + +To access the private flash chip, we can use a ch341a based flash programmer and +flash the chip with the AC adapter disconnected. + +To flash coreboot on a board running OME firmware, create a backup for both flash +chips, then do the following: + +1. Erase the private flash to disable the IFD protection +2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside + the protected flash region + +To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, +then run: + + flashrom -p --erase + +To modify the IFD, write the following flash layout to a file: + + 00000000:00000fff fd + 00001000:00002fff gbe + 00003000:005fffff me + 00600000:00bfffff bios + 00eb5000:00ffffff pd + +Suppose the above layout file is ``layout.txt`` and the origin content of the system flash +is in ``factory-sys.rom``, run: + + ifdtool -n layout.txt factory-sys.rom + +Then a flash image with a new IFD will be in ``factory-sys.rom.new``. + +Flash the IFD of the system flash: + + flashrom -p --ifd -i fd -w factory-sys.rom.new + +Then flash the coreboot image: + + # first extend the 12M coreboot.rom to 16M + fallocate -l 16M build/coreboot.rom + flashrom -p --ifd -i bios -w build/coreboot.rom + +After coreboot is installed, the coreboot firmware can be updated with internal flashing: + + flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left. + +## Test status + +### Untested + +- NFC module +- Fingerprint reader +- Smart Card reader + +### Working + +- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory +- SATA and M.2 SATA disk +- PCIe SSD +- Webcam +- Touch screen +- Audio output from speaker and headphone jack +- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards]) +- WLAN +- WWAN +- SD card reader +- Internal LCD, DisplayPort and VGA video outputs +- Dock +- USB +- Keyboard and touchpad +- EC ACPI +- S3 resume +- TPM +- Arch Linux with Linux 5.11.16 +- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1 +- Graphics initialization with libgfxinit +- Payload: SeaBIOS 1.16.2 +- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05 +- Internal flashing under coreboot + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| SoC | Intel Broadwell | ++------------------+-----------------------------+ +| EC | SMSC MEC1324 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/ +[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf +[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog +[HP Sure Start]: hp_sure_start.md diff --git a/Documentation/mainboard/hp/elitebook_820_g2_flash.jpg b/Documentation/mainboard/hp/elitebook_820_g2_flash.jpg new file mode 100644 index 0000000000000000000000000000000000000000..17115278ba5df59fa97b9cd67488701d299ef22d GIT binary patch literal 86225 zcmb4qRZyJI6YVap!51eu3oHb8cXxLd3AVTd3l<3OZo%CaSuD6)@IbNz2tk4q90L4q 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a/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl new file mode 100644 index 0000000000..8023ae826c --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/elitebook_820_g2/acpi/superio.asl b/src/mainboard/hp/elitebook_820_g2/acpi/superio.asl new file mode 100644 index 0000000000..55b1db5b11 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/src/mainboard/hp/elitebook_820_g2/board_info.txt b/src/mainboard/hp/elitebook_820_g2/board_info.txt new file mode 100644 index 0000000000..eec345937f --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/ +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/hp/elitebook_820_g2/data.vbt b/src/mainboard/hp/elitebook_820_g2/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..563cdbad0fda31890ca0bbea47d3dbc2f0d8d524 GIT binary patch literal 4493 zcmdT{Z)g)|7=P|Ae=e81OLDE6X4<{2MboZ-uAz3FbnKF*T~bq*QklkEwi<) z(y@VY>pT{MK+(~ zd7nS`yuZAEp7(ik4WpqE5(y@@_Qqnwq%^4Tsb>YYFS;HrTU?d=D#O zhv(i+fHcFb6x-DfHM)N~ll2cbl1O4J85rNSFPmu#XQtks9-kobo+t_K-kr&2CU;I} z(j+nZYLHM&NeCU>mravVYLM4Av~FmnSUX6&+NQqL7Es$aNJ6-`XK)}MjRi-dgPY0V zFbPK!!9=2WAQXFz#D@nX(NJ`xH(WmIqNitk;@!!8d*7TU{+>n>P*t@Bk=uzrWYRM} zInhdj*(@2RF;iqXGnJVigBs}Q?Aq9^g~EN2{#bl?WHh;Ld+x{wAI|#V?uDga(q~RhnNcAs)WRg^hcg@t zUvXV9U|E3Q9Ry^-4Ry#J$YXXM&e|3D2Kh4b&&Yq+1^5e@-v&KSw@^d=~j@+RQF$1l=r7494-l(hGZqq#bkBNq*ew8;&qy5HVgj-Q7}>TB-mtk?W(Ry0s zpvA6o@?iBdNfGsAE}GS+!R9jzdw0?Ku>3FItlWgD!s)evFO@fSRtAXm#mC}1_h+)3 zcfOOU&{!3LbPZ@hSf_fAb{g~as!ecW2vkj-s4_gY=h|i#hkWa_jUQ^@4n8%IX9yV20$x$Z)66VsK8o_3 zm$`-o_?rDTbF}LJsnLaUFZ0kCz;f#`$*`ZSUEK-S9l1PNT;t|b^#)dLC7v}MI9i5r z@T}D$md3!Ni)fZ$wa8PIwea5RFjXx)Q`e9Z`C1RSN@-_ydwx4Yu?#qX2NwT!SU|*` z3_}EhC19ZM7^p*61XUwMcSSHV1r6ZGJkX3N3knTQ2Rf}l2)Nk$fc{1Gd+~>-^cTjh z2-q9oJW}H^;8r_H$f=Atg*TjJ)~OtK3Uf|!$*KJ06n=9OUQ~Rd&>)h2QQ0mEdqnby zsGJssb0WDaDvP3UQzULlsh5Oii403hS`zk4r@!DFK(z?UI^UYmQxHavnUmcs%$?5z{-#in_eb zxKUbN>oHl%_YzMOFm$dW;gam~2y-q1?a9@|pR1<50BSoAv$$SJA}!s^Bb1j2deV(k zP4}B3bU$(yIjm7U?mmI;-(Mg;$)R7sy(!qz7AX-&m)c@XYbPU;n8Q4 z-I((p=xWiDElYdBflEig5@uWeTr_Hs%0X4i?e@@K#u%`gB8e4V;m=GMoz#Q$!U3@L xyVpbVeE$M|Pdt@Y|7f_cX + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include + + #include + #include "acpi/platform.asl" + #include + + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } +} diff --git a/src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads b/src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads new file mode 100644 index 0000000000..3962512eec --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- All DisplayPorts + HDMI1, + DP2, -- VGA + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/elitebook_820_g2/gpio.c b/src/mainboard/hp/elitebook_820_g2/gpio.c new file mode 100644 index 0000000000..8eb7bfd50c --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = LP_GPIO_OUT_LOW, + [3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = LP_GPIO_OUT_HIGH, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = LP_GPIO_OUT_HIGH, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .reset = GPIO_RESET_RSMRST }, + [25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_HIGH, + [29] = LP_GPIO_OUT_LOW, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [35] = LP_GPIO_NATIVE, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [37] = LP_GPIO_NATIVE, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [48] = LP_GPIO_OUT_HIGH, + [49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_HIGH, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [53] = LP_GPIO_OUT_HIGH, + [54] = LP_GPIO_OUT_HIGH, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .owner = GPIO_OWNER_GPIO, .irqen = GPIO_IRQ_ENABLE, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_LOW, + [58] = LP_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_HIGH, + [61] = LP_GPIO_OUT_LOW, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = LP_GPIO_OUT_LOW, + [66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_NATIVE, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_NATIVE, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = LP_GPIO_OUT_LOW, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_OUT_HIGH, + [83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/elitebook_820_g2/hda_verb.c b/src/mainboard/hp/elitebook_820_g2/hda_verb.c new file mode 100644 index 0000000000..7199d3f827 --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/hda_verb.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c225a, /* Subsystem ID */ + 57, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(0, 0x103c198f), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0421101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x04a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40748605), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x02050007, 0x0204c200, 0x02050063, 0x02044800, + 0x02050066, 0x02040809, 0x02050015, 0x02048842, + 0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd, + 0x02050065, 0x02042000, 0x0205001c, 0x0204c900, + 0x02050018, 0x02043788, 0x02050008, 0x02048210, + 0x02050068, 0x02043022, 0x02050006, 0x02040800, + 0x02050061, 0x02040403, 0x02050061, 0x02040403, + 0x0205005f, 0x02040800, 0x02050060, 0x02040800, + 0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4, + 0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8, + 0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad, + 0x02050036, 0x0204cbd2, 0x02050037, 0x02041605, + 0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f, + 0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54, + 0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000, + 0x02050030, 0x02041f5c, 0x02050031, 0x02040111, + 0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9, + 0x0205002f, 0x02040000, 0x02050042, 0x0204c66e, + 0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad, + 0x02050044, 0x0204ccdd, 0x02050045, 0x02041549, + 0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79, + 0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54, + 0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000, + 0x0205003f, 0x02041f4d, 0x02050040, 0x02040129, + 0x02050041, 0x02041f51, 0x02050049, 0x02041f61, + 0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4, + 0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad, + 0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98, + 0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e, + 0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54, + 0x02050053, 0x02040b73, 0x0205003d, 0x02040000, + 0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a, + 0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0, + 0x0205002f, 0x02040000, 0x02050058, 0x0204c17a, + 0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad, + 0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e, + 0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899, + 0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54, + 0x0205005e, 0x02041444, 0x0205003d, 0x02040000, + 0x02050055, 0x02041fd8, 0x02050056, 0x02040045, + 0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2, + 0x02050026, 0x02042828, 0x02050029, 0x02040250, + 0x02050004, 0x0204c09e, 0x0205000e, 0x02045001, +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/elitebook_820_g2/pei_data.c b/src/mainboard/hp/elitebook_820_g2/pei_data.c new file mode 100644 index 0000000000..a31f2112cc --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/pei_data.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 1; + + /* P1 */ + pei_data_usb2_port(pei_data, 0, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P2: left side port, USB debug */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P3: digitizer and right side ports (Microchip hub) */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P4: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P5: fingerprint reader */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P6: WWAN */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P7: webcam */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + /* P8 */ + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL); + + /* P1 */ + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + /* P2: left side, USB debug */ + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + /* P3: right side (Microchip hub) */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4 */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +}