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CK804: Cosmetic fixes, switch to u8 et al. 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2011-01-04 17:36:55 +00:00
parent ecab12a09e
commit 7e2fbd5dd3
17 changed files with 83 additions and 86 deletions
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4
src/southbridge/nvidia/ck804/chip.h
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@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef CK804_CHIP_H #ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H
#define CK804_CHIP_H #define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H
struct southbridge_nvidia_ck804_config { struct southbridge_nvidia_ck804_config {
unsigned int usb1_hc_reset : 1; unsigned int usb1_hc_reset : 1;

8
src/southbridge/nvidia/ck804/ck804.c
View File

@ -26,7 +26,7 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "ck804.h" #include "ck804.h"
static uint32_t final_reg; static u32 final_reg;
static device_t find_lpc_dev(device_t dev, unsigned devfn) static device_t find_lpc_dev(device_t dev, unsigned devfn)
{ {
@ -41,7 +41,7 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn)
&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO) && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)
&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE))) && (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))
{ {
uint32_t id; u32 id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
if ((id != (PCI_VENDOR_ID_NVIDIA | if ((id != (PCI_VENDOR_ID_NVIDIA |
(PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16))) (PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))
@ -61,8 +61,8 @@ void ck804_enable(device_t dev)
{ {
device_t lpc_dev; device_t lpc_dev;
unsigned index = 0, index2 = 0, deviceid, vendorid, devfn; unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
uint32_t reg_old, reg; u32 reg_old, reg;
uint8_t byte; u8 byte;
struct southbridge_nvidia_ck804_config *conf; struct southbridge_nvidia_ck804_config *conf;
conf = dev->chip_info; conf = dev->chip_info;

4
src/southbridge/nvidia/ck804/ck804.h
View File

@ -18,8 +18,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef CK804_H #ifndef SOUTHBRIDGE_NVIDIA_CK804_CK804_H
#define CK804_H #define SOUTHBRIDGE_NVIDIA_CK804_CK804_H
#include "chip.h" #include "chip.h"

6
src/southbridge/nvidia/ck804/early_setup.c
View File

@ -20,7 +20,7 @@
#include <reset.h> #include <reset.h>
static int set_ht_link_ck804(uint8_t ht_c_num) static int set_ht_link_ck804(u8 ht_c_num)
{ {
unsigned vendorid = 0x10de; unsigned vendorid = 0x10de;
unsigned val = 0x01610169; unsigned val = 0x01610169;
@ -91,7 +91,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
static void ck804_early_set_port(void) static void ck804_early_set_port(void)
{ {
static const unsigned int ctrl_devport_conf[] = { static const unsigned int ctrl_devport_conf[] = {
PCI_ADDR(0, (CK804_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, PCI_ADDR(0, (CK804_DEVN_BASE + 0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
#if CONFIG_CK804_NUM > 1 #if CONFIG_CK804_NUM > 1
PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE, PCI_ADDR(CK804B_BUSN, (CK804B_DEVN_BASE+0x1), 0, ANACTRL_REG_POS), ~(0x0000ff00), CK804B_ANACTRL_IO_BASE,
#endif #endif
@ -229,7 +229,7 @@ static void ck804_early_setup(void)
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xd0), ~(0xf0000000), 0x00000000,
RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000, RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 8, 0, 0xe0), ~(0xf0000000), 0x00000000,
#if CONFIG_CK804_NUM > 1 #if CONFIG_CK804_NUM > 1
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000, RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 8, 0, 0x68), ~(0x02000000), 0x02000000,

27
src/southbridge/nvidia/ck804/early_setup_car.c
View File

@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
static int set_ht_link_ck804(uint8_t ht_c_num) static int set_ht_link_ck804(u8 ht_c_num)
{ {
unsigned vendorid = 0x10de; unsigned vendorid = 0x10de;
unsigned val = 0x01610169; unsigned val = 0x01610169;
@ -89,13 +89,12 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
int j; int j;
for (j = 0; j < ck804_num; j++) { for (j = 0; j < ck804_num; j++) {
u32 dev; u32 dev;
if (busn[j] == 0) //sb chain if (busn[j] == 0) /* SB chain */
dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0);
else else
dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0);
setup_resource_map_offset(ctrl_devport_conf, setup_resource_map_offset(ctrl_devport_conf,
ARRAY_SIZE(ctrl_devport_conf), dev, ARRAY_SIZE(ctrl_devport_conf), dev, io_base[j]);
io_base[j]);
} }
} }
@ -110,13 +109,12 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
int j; int j;
for (j = 0; j < ck804_num; j++) { for (j = 0; j < ck804_num; j++) {
u32 dev; u32 dev;
if (busn[j] == 0) //sb chain if (busn[j] == 0) /* SB chain */
dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0); dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0);
else else
dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0); dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0);
setup_resource_map_offset(ctrl_devport_conf_clear, setup_resource_map_offset(ctrl_devport_conf_clear,
ARRAY_SIZE(ctrl_devport_conf_clear), dev, ARRAY_SIZE(ctrl_devport_conf_clear), dev, io_base[j]);
io_base[j]);
} }
} }
@ -165,7 +163,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
/* Activate master port on primary SATA controller. */ /* Activate master port on primary SATA controller. */
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013, RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x50), ~(0x1f000013), 0x15000013,
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001, RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x64), ~(0x00000001), 0x00000001,
RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000, RES_PCI_IO, PCI_ADDR(0, 7, 0, 0x68), ~(0x02000000), 0x02000000,
@ -196,7 +194,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
//SYSCTRL /* SYSCTRL */
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
#if CONFIG_CK804_USE_NIC #if CONFIG_CK804_USE_NIC
@ -211,7 +209,6 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
#endif #endif
}; };
static const unsigned int ctrl_conf_multiple[] = { static const unsigned int ctrl_conf_multiple[] = {
@ -267,7 +264,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, ~(0xfffff), (0x1c << 10) | 0x1b,
/* This line doesn't exist in the non-CAR version. */ /* This line doesn't exist in the non-CAR version. */
RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000,
RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8),
@ -296,8 +293,8 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
} }
setup_resource_map_x_offset(ctrl_conf_slave, setup_resource_map_x_offset(ctrl_conf_slave,
ARRAY_SIZE(ctrl_conf_slave), ARRAY_SIZE(ctrl_conf_slave),
PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]); PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]);
} }
for (j = 0; j < ck804_num; j++) { for (j = 0; j < ck804_num; j++) {
@ -325,9 +322,9 @@ static int ck804_early_setup_x(void)
int i, ck804_num = 0; int i, ck804_num = 0;
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
uint32_t id; u32 id;
device_t dev; device_t dev;
if (i == 0) // SB chain if (i == 0) /* SB chain */
dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0); dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0);
else else
dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0); dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0);

2
src/southbridge/nvidia/ck804/early_smbus.c
View File

@ -64,7 +64,7 @@ int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address)
} }
int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address,
unsigned char val) unsigned char val)
{ {
return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val);
} }

6
src/southbridge/nvidia/ck804/ide.c
View File

@ -28,9 +28,9 @@
static void ide_init(struct device *dev) static void ide_init(struct device *dev)
{ {
struct southbridge_nvidia_ck804_config *conf; struct southbridge_nvidia_ck804_config *conf;
uint32_t dword; u32 dword;
uint16_t word; u16 word;
uint8_t byte; u8 byte;
conf = dev->chip_info; conf = dev->chip_info;

44
src/southbridge/nvidia/ck804/lpc.c
View File

@ -53,16 +53,16 @@
static void lpc_common_init(device_t dev) static void lpc_common_init(device_t dev)
{ {
uint8_t byte; u8 byte;
uint32_t dword; u32 dword;
/* I/O APIC initialization */ /* I/O APIC initialization. */
byte = pci_read_config8(dev, 0x74); byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable APIC. */ byte |= (1 << 0); /* Enable APIC. */
pci_write_config8(dev, 0x74, byte); pci_write_config8(dev, 0x74, byte);
dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */ dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
setup_ioapic(dword, 0); // Don't rename IOAPIC ID setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */
#if 1 #if 1
dword = pci_read_config32(dev, 0xe4); dword = pci_read_config32(dev, 0xe4);
@ -78,8 +78,8 @@ static void lpc_slave_init(device_t dev)
static void rom_dummy_write(device_t dev) static void rom_dummy_write(device_t dev)
{ {
uint8_t old, new; u8 old, new;
uint8_t *p; u8 *p;
old = pci_read_config8(dev, 0x88); old = pci_read_config8(dev, 0x88);
new = old | 0xc0; new = old | 0xc0;
@ -92,7 +92,7 @@ static void rom_dummy_write(device_t dev)
pci_write_config8(dev, 0x6d, new); pci_write_config8(dev, 0x6d, new);
/* Dummy write. */ /* Dummy write. */
p = (uint8_t *) 0xffffffe0; p = (u8 *) 0xffffffe0;
old = 0; old = 0;
*p = old; *p = old;
old = *p; old = *p;
@ -113,11 +113,11 @@ static void enable_hpet(struct device *dev)
printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address);
} }
unsigned pm_base=0; unsigned pm_base = 0;
static void lpc_init(device_t dev) static void lpc_init(device_t dev)
{ {
uint8_t byte, byte_old; u8 byte, byte_old;
int on, nmi_option; int on, nmi_option;
lpc_common_init(dev); lpc_common_init(dev);
@ -125,7 +125,7 @@ static void lpc_init(device_t dev)
pm_base = pci_read_config32(dev, 0x60) & 0xff00; pm_base = pci_read_config32(dev, 0x60) & 0xff00;
printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
#if CK804_CHIP_REV==1 #if CK804_CHIP_REV == 1
if (dev->bus->secondary != 1) if (dev->bus->secondary != 1)
return; return;
#endif #endif
@ -136,7 +136,7 @@ static void lpc_init(device_t dev)
pci_write_config8(dev, 0x46, byte | (1 << 0)); pci_write_config8(dev, 0x46, byte | (1 << 0));
#endif #endif
/* power after power fail */ /* Power after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail"); get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
@ -150,18 +150,17 @@ static void lpc_init(device_t dev)
on = SLOW_CPU_OFF; on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu"); get_option(&on, "slow_cpu");
if (on) { if (on) {
uint16_t pm10_bar; u16 pm10_bar;
uint32_t dword; u32 dword;
pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00); pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
outl(((on << 1) + 0x10), (pm10_bar + 0x10)); outl(((on << 1) + 0x10), (pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10); dword = inl(pm10_bar + 0x10);
on = 8 - on; on = 8 - on;
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
(on * 12) + (on >> 1), (on & 1) * 5); (on * 12) + (on >> 1), (on & 1) * 5);
} }
#if 0 #if 0
// default is enabled /* Enable Port 92 fast reset (default is enabled). */
/* Enable Port 92 fast reset. */
byte = pci_read_config8(dev, 0xe8); byte = pci_read_config8(dev, 0xe8);
byte |= ~(1 << 3); byte |= ~(1 << 3);
pci_write_config8(dev, 0xe8, byte); pci_write_config8(dev, 0xe8, byte);
@ -178,11 +177,10 @@ static void lpc_init(device_t dev)
byte_old = byte; byte_old = byte;
nmi_option = NMI_OFF; nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi"); get_option(&nmi_option, "nmi");
if (nmi_option) { if (nmi_option)
byte &= ~(1 << 7); /* Set NMI. */ byte &= ~(1 << 7); /* Set NMI. */
} else { else
byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */ byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
}
if (byte != byte_old) if (byte != byte_old)
outb(byte, 0x70); outb(byte, 0x70);
@ -236,12 +234,11 @@ static void ck804_lpc_read_resources(device_t dev)
* *
* This function is called by the global enable_resources() indirectly via the * This function is called by the global enable_resources() indirectly via the
* device_operation::enable_resources() method of devices. * device_operation::enable_resources() method of devices.
*
*/ */
static void ck804_lpc_enable_childrens_resources(device_t dev) static void ck804_lpc_enable_childrens_resources(device_t dev)
{ {
struct bus *link; struct bus *link;
uint32_t reg, reg_var[4]; u32 reg, reg_var[4];
int i, var_num = 0; int i, var_num = 0;
reg = pci_read_config32(dev, 0xa0); reg = pci_read_config32(dev, 0xa0);
@ -252,7 +249,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res; struct resource *res;
for (res = child->resource_list; res; res = res->next) { for (res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long unsigned long base, end; /* Don't need long long. */
if (!(res->flags & IORESOURCE_IO)) if (!(res->flags & IORESOURCE_IO))
continue; continue;
base = res->base; base = res->base;
@ -279,8 +276,9 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
break; break;
} }
if (base == 0x290 || base >= 0x400) { if (base == 0x290 || base >= 0x400) {
/* Only 4 var; compact them? */
if (var_num >= 4) if (var_num >= 4)
continue; // only 4 var ; compact them ? continue;
reg |= (1 << (28 + var_num)); reg |= (1 << (28 + var_num));
reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16); reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
} }

4
src/southbridge/nvidia/ck804/nic.c
View File

@ -29,10 +29,10 @@
static void nic_init(struct device *dev) static void nic_init(struct device *dev)
{ {
uint32_t dword, old, mac_h, mac_l; u32 dword, old, mac_h, mac_l;
int eeprom_valid = 0; int eeprom_valid = 0;
struct southbridge_nvidia_ck804_config *conf; struct southbridge_nvidia_ck804_config *conf;
static uint32_t nic_index = 0; static u32 nic_index = 0;
unsigned long base; unsigned long base;
struct resource *res; struct resource *res;

2
src/southbridge/nvidia/ck804/pci.c
View File

@ -28,7 +28,7 @@
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
{ {
uint32_t dword; u32 dword;
device_t pci_domain_dev; device_t pci_domain_dev;
struct resource *mem, *pref; struct resource *mem, *pref;

2
src/southbridge/nvidia/ck804/pcie.c
View File

@ -27,7 +27,7 @@
static void pcie_init(struct device *dev) static void pcie_init(struct device *dev)
{ {
uint32_t dword; u32 dword;
/* Enable PCI error detecting. */ /* Enable PCI error detecting. */
dword = pci_read_config32(dev, 0x04); dword = pci_read_config32(dev, 0x04);

9
src/southbridge/nvidia/ck804/sata.c
View File

@ -35,11 +35,11 @@ static void sata_com_reset(struct device *dev, unsigned reset)
// reset = 1 : reset // reset = 1 : reset
// reset = 0 : clear // reset = 0 : clear
{ {
uint32_t *base; u32 *base;
uint32_t dword; u32 dword;
int loop; int loop;
base = (uint32_t *) pci_read_config32(dev, 0x24); base = (u32 *) pci_read_config32(dev, 0x24);
printk(BIOS_DEBUG, "base = %08lx\n", base); printk(BIOS_DEBUG, "base = %08lx\n", base);
@ -95,7 +95,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
static void sata_init(struct device *dev) static void sata_init(struct device *dev)
{ {
uint32_t dword; u32 dword;
struct southbridge_nvidia_ck804_config *conf; struct southbridge_nvidia_ck804_config *conf;
conf = dev->chip_info; conf = dev->chip_info;
@ -161,7 +161,6 @@ static void sata_init(struct device *dev)
sata_com_reset(dev, 1); /* For discover some s-atapi device. */ sata_com_reset(dev, 1); /* For discover some s-atapi device. */
#endif #endif
} }
static struct device_operations sata_ops = { static struct device_operations sata_ops = {

6
src/southbridge/nvidia/ck804/smbus.c
View File

@ -43,7 +43,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device); return do_smbus_recv_byte(res->base, device);
} }
static int lsmbus_send_byte(device_t dev, uint8_t val) static int lsmbus_send_byte(device_t dev, u8 val)
{ {
unsigned device; unsigned device;
struct resource *res; struct resource *res;
@ -57,7 +57,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
return do_smbus_send_byte(res->base, device, val); return do_smbus_send_byte(res->base, device, val);
} }
static int lsmbus_read_byte(device_t dev, uint8_t address) static int lsmbus_read_byte(device_t dev, u8 address)
{ {
unsigned device; unsigned device;
struct resource *res; struct resource *res;
@ -71,7 +71,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
return do_smbus_read_byte(res->base, device, address); return do_smbus_read_byte(res->base, device, address);
} }
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
{ {
unsigned device; unsigned device;
struct resource *res; struct resource *res;

12
src/southbridge/nvidia/ck804/smbus.h
View File

@ -90,7 +90,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
outb(0, smbus_io_base + SMBHSTCMD); outb(0, smbus_io_base + SMBHSTCMD);
smbus_delay(); smbus_delay();
/* Byte data recv */ /* Byte data recv. */
outb(0x05, smbus_io_base + SMBHSTPRTCL); outb(0x05, smbus_io_base + SMBHSTPRTCL);
smbus_delay(); smbus_delay();
@ -98,7 +98,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
if (smbus_wait_until_done(smbus_io_base) < 0) if (smbus_wait_until_done(smbus_io_base) < 0)
return -3; return -3;
/* Lose check */ /* Lose check. */
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
/* Read results of transaction. */ /* Read results of transaction. */
@ -140,7 +140,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
if (smbus_wait_until_done(smbus_io_base) < 0) if (smbus_wait_until_done(smbus_io_base) < 0)
return -3; return -3;
/* Lose check */ /* Lose check. */
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
if (global_status_register != 0x80) if (global_status_register != 0x80)
@ -169,7 +169,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
outb(address & 0xff, smbus_io_base + SMBHSTCMD); outb(address & 0xff, smbus_io_base + SMBHSTCMD);
smbus_delay(); smbus_delay();
/* Byte data read */ /* Byte data read. */
outb(0x07, smbus_io_base + SMBHSTPRTCL); outb(0x07, smbus_io_base + SMBHSTPRTCL);
smbus_delay(); smbus_delay();
@ -177,7 +177,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
if (smbus_wait_until_done(smbus_io_base) < 0) if (smbus_wait_until_done(smbus_io_base) < 0)
return -3; return -3;
/* Lose check */ /* Lose check. */
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
/* Read results of transaction. */ /* Read results of transaction. */
@ -219,7 +219,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
if (smbus_wait_until_done(smbus_io_base) < 0) if (smbus_wait_until_done(smbus_io_base) < 0)
return -3; return -3;
/* Lose check */ /* Lose check. */
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80; global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
if (global_status_register != 0x80) if (global_status_register != 0x80)

28
src/southbridge/nvidia/ck804/usb.c
View File

@ -28,20 +28,22 @@
static void usb1_init(struct device *dev) static void usb1_init(struct device *dev)
{ {
struct southbridge_nvidia_ck804_config const *conf = dev->chip_info; struct southbridge_nvidia_ck804_config const *conf = dev->chip_info;
if (conf->usb1_hc_reset) {
/*
* Somehow the warm reset does not really reset the USB
* controller. Later, during boot, when the Bus Master bit is
* set, the USB controller trashes the memory, causing weird
* misbehavior. Was detected on Sun Ultra40, where mptable
* was damaged.
*/
uint32_t bar0 = pci_read_config32(dev, 0x10);
uint32_t *regs = (uint32_t *) (bar0 & ~0xfff);
/* OHCI USB HCCommandStatus Register, HostControllerReset bit */ if (!conf->usb1_hc_reset)
regs[2] |= 1; return;
}
/*
* Somehow the warm reset does not really reset the USB
* controller. Later, during boot, when the Bus Master bit is
* set, the USB controller trashes the memory, causing weird
* misbehavior. Was detected on Sun Ultra40, where mptable
* was damaged.
*/
u32 bar0 = pci_read_config32(dev, 0x10);
u32 *regs = (u32 *) (bar0 & ~0xfff);
/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
regs[2] |= 1;
} }
static struct device_operations usb_ops = { static struct device_operations usb_ops = {

3
src/southbridge/nvidia/ck804/usb2.c
View File

@ -27,7 +27,8 @@
static void usb2_init(struct device *dev) static void usb2_init(struct device *dev)
{ {
uint32_t dword; u32 dword;
dword = pci_read_config32(dev, 0xf8); dword = pci_read_config32(dev, 0xf8);
dword |= 40; dword |= 40;
pci_write_config32(dev, 0xf8, dword); pci_write_config32(dev, 0xf8, dword);