CK804: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
ecab12a09e
commit
7e2fbd5dd3
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@ -18,8 +18,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CK804_CHIP_H
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#define CK804_CHIP_H
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#ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H
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#define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H
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struct southbridge_nvidia_ck804_config {
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unsigned int usb1_hc_reset : 1;
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@ -26,7 +26,7 @@
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#include <device/pci_ops.h>
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#include "ck804.h"
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static uint32_t final_reg;
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static u32 final_reg;
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static device_t find_lpc_dev(device_t dev, unsigned devfn)
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{
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@ -41,7 +41,7 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn)
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&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_PRO)
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&& (lpc_dev->device != PCI_DEVICE_ID_NVIDIA_CK804_SLAVE)))
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{
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uint32_t id;
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u32 id;
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id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
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if ((id != (PCI_VENDOR_ID_NVIDIA |
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(PCI_DEVICE_ID_NVIDIA_CK804_LPC << 16)))
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@ -61,8 +61,8 @@ void ck804_enable(device_t dev)
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{
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device_t lpc_dev;
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unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
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uint32_t reg_old, reg;
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uint8_t byte;
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u32 reg_old, reg;
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u8 byte;
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struct southbridge_nvidia_ck804_config *conf;
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conf = dev->chip_info;
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@ -18,8 +18,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CK804_H
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#define CK804_H
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#ifndef SOUTHBRIDGE_NVIDIA_CK804_CK804_H
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#define SOUTHBRIDGE_NVIDIA_CK804_CK804_H
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#include "chip.h"
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@ -20,7 +20,7 @@
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#include <reset.h>
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static int set_ht_link_ck804(uint8_t ht_c_num)
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static int set_ht_link_ck804(u8 ht_c_num)
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{
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unsigned vendorid = 0x10de;
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unsigned val = 0x01610169;
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@ -18,7 +18,7 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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static int set_ht_link_ck804(uint8_t ht_c_num)
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static int set_ht_link_ck804(u8 ht_c_num)
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{
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unsigned vendorid = 0x10de;
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unsigned val = 0x01610169;
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@ -89,13 +89,12 @@ static void ck804_early_set_port(unsigned ck804_num, unsigned *busn,
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int j;
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for (j = 0; j < ck804_num; j++) {
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u32 dev;
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if (busn[j] == 0) //sb chain
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if (busn[j] == 0) /* SB chain */
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dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0);
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else
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dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0);
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setup_resource_map_offset(ctrl_devport_conf,
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ARRAY_SIZE(ctrl_devport_conf), dev,
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io_base[j]);
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ARRAY_SIZE(ctrl_devport_conf), dev, io_base[j]);
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}
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}
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@ -110,13 +109,12 @@ static void ck804_early_clear_port(unsigned ck804_num, unsigned *busn,
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int j;
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for (j = 0; j < ck804_num; j++) {
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u32 dev;
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if (busn[j] == 0) //sb chain
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if (busn[j] == 0) /* SB chain */
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dev = PCI_DEV(busn[j], CK804_DEVN_BASE, 0);
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else
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dev = PCI_DEV(busn[j], CK804B_DEVN_BASE, 0);
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setup_resource_map_offset(ctrl_devport_conf_clear,
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ARRAY_SIZE(ctrl_devport_conf_clear), dev,
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io_base[j]);
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ARRAY_SIZE(ctrl_devport_conf_clear), dev, io_base[j]);
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}
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}
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@ -196,7 +194,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
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RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8),
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//SYSCTRL
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/* SYSCTRL */
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)),
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)),
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#if CONFIG_CK804_USE_NIC
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@ -211,7 +209,6 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)),
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#endif
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};
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static const unsigned int ctrl_conf_multiple[] = {
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@ -325,9 +322,9 @@ static int ck804_early_setup_x(void)
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int i, ck804_num = 0;
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for (i = 0; i < 4; i++) {
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uint32_t id;
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u32 id;
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device_t dev;
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if (i == 0) // SB chain
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if (i == 0) /* SB chain */
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dev = PCI_DEV(i * 0x40, CK804_DEVN_BASE, 0);
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else
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dev = PCI_DEV(i * 0x40, CK804B_DEVN_BASE, 0);
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@ -28,9 +28,9 @@
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static void ide_init(struct device *dev)
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{
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struct southbridge_nvidia_ck804_config *conf;
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uint32_t dword;
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uint16_t word;
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uint8_t byte;
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u32 dword;
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u16 word;
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u8 byte;
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conf = dev->chip_info;
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@ -53,16 +53,16 @@
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static void lpc_common_init(device_t dev)
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{
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uint8_t byte;
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uint32_t dword;
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u8 byte;
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u32 dword;
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/* I/O APIC initialization */
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/* I/O APIC initialization. */
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byte = pci_read_config8(dev, 0x74);
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byte |= (1 << 0); /* Enable APIC. */
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pci_write_config8(dev, 0x74, byte);
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dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
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setup_ioapic(dword, 0); // Don't rename IOAPIC ID
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setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */
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#if 1
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dword = pci_read_config32(dev, 0xe4);
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@ -78,8 +78,8 @@ static void lpc_slave_init(device_t dev)
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static void rom_dummy_write(device_t dev)
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{
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uint8_t old, new;
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uint8_t *p;
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u8 old, new;
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u8 *p;
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old = pci_read_config8(dev, 0x88);
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new = old | 0xc0;
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@ -92,7 +92,7 @@ static void rom_dummy_write(device_t dev)
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pci_write_config8(dev, 0x6d, new);
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/* Dummy write. */
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p = (uint8_t *) 0xffffffe0;
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p = (u8 *) 0xffffffe0;
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old = 0;
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*p = old;
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old = *p;
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@ -117,7 +117,7 @@ unsigned pm_base=0;
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static void lpc_init(device_t dev)
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{
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uint8_t byte, byte_old;
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u8 byte, byte_old;
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int on, nmi_option;
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lpc_common_init(dev);
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@ -136,7 +136,7 @@ static void lpc_init(device_t dev)
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pci_write_config8(dev, 0x46, byte | (1 << 0));
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#endif
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/* power after power fail */
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/* Power after power fail */
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on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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get_option(&on, "power_on_after_fail");
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byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
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@ -150,8 +150,8 @@ static void lpc_init(device_t dev)
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on = SLOW_CPU_OFF;
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get_option(&on, "slow_cpu");
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if (on) {
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uint16_t pm10_bar;
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uint32_t dword;
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u16 pm10_bar;
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u32 dword;
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pm10_bar = (pci_read_config16(dev, 0x60) & 0xff00);
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outl(((on << 1) + 0x10), (pm10_bar + 0x10));
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dword = inl(pm10_bar + 0x10);
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@ -160,8 +160,7 @@ static void lpc_init(device_t dev)
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(on * 12) + (on >> 1), (on & 1) * 5);
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}
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#if 0
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// default is enabled
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/* Enable Port 92 fast reset. */
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/* Enable Port 92 fast reset (default is enabled). */
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byte = pci_read_config8(dev, 0xe8);
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byte |= ~(1 << 3);
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pci_write_config8(dev, 0xe8, byte);
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@ -178,11 +177,10 @@ static void lpc_init(device_t dev)
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byte_old = byte;
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nmi_option = NMI_OFF;
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get_option(&nmi_option, "nmi");
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if (nmi_option) {
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if (nmi_option)
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byte &= ~(1 << 7); /* Set NMI. */
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} else {
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else
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byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
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}
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if (byte != byte_old)
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outb(byte, 0x70);
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@ -236,12 +234,11 @@ static void ck804_lpc_read_resources(device_t dev)
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*
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* This function is called by the global enable_resources() indirectly via the
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* device_operation::enable_resources() method of devices.
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*
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*/
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static void ck804_lpc_enable_childrens_resources(device_t dev)
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{
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struct bus *link;
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uint32_t reg, reg_var[4];
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u32 reg, reg_var[4];
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int i, var_num = 0;
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reg = pci_read_config32(dev, 0xa0);
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@ -252,7 +249,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
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if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
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struct resource *res;
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for (res = child->resource_list; res; res = res->next) {
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unsigned long base, end; // don't need long long
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unsigned long base, end; /* Don't need long long. */
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if (!(res->flags & IORESOURCE_IO))
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continue;
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base = res->base;
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@ -279,8 +276,9 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
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break;
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}
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if (base == 0x290 || base >= 0x400) {
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/* Only 4 var; compact them? */
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if (var_num >= 4)
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continue; // only 4 var ; compact them ?
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continue;
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reg |= (1 << (28 + var_num));
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reg_var[var_num++] = (base & 0xffff) | ((end & 0xffff) << 16);
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}
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@ -29,10 +29,10 @@
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static void nic_init(struct device *dev)
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{
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uint32_t dword, old, mac_h, mac_l;
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u32 dword, old, mac_h, mac_l;
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int eeprom_valid = 0;
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struct southbridge_nvidia_ck804_config *conf;
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static uint32_t nic_index = 0;
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static u32 nic_index = 0;
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unsigned long base;
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struct resource *res;
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@ -28,7 +28,7 @@
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static void pci_init(struct device *dev)
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{
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uint32_t dword;
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u32 dword;
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device_t pci_domain_dev;
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struct resource *mem, *pref;
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@ -27,7 +27,7 @@
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static void pcie_init(struct device *dev)
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{
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uint32_t dword;
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u32 dword;
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/* Enable PCI error detecting. */
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dword = pci_read_config32(dev, 0x04);
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@ -35,11 +35,11 @@ static void sata_com_reset(struct device *dev, unsigned reset)
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// reset = 1 : reset
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// reset = 0 : clear
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{
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uint32_t *base;
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uint32_t dword;
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u32 *base;
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u32 dword;
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int loop;
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base = (uint32_t *) pci_read_config32(dev, 0x24);
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base = (u32 *) pci_read_config32(dev, 0x24);
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printk(BIOS_DEBUG, "base = %08lx\n", base);
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@ -95,7 +95,7 @@ static void sata_com_reset(struct device *dev, unsigned reset)
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static void sata_init(struct device *dev)
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{
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uint32_t dword;
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u32 dword;
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struct southbridge_nvidia_ck804_config *conf;
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conf = dev->chip_info;
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@ -161,7 +161,6 @@ static void sata_init(struct device *dev)
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sata_com_reset(dev, 1); /* For discover some s-atapi device. */
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#endif
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}
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static struct device_operations sata_ops = {
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@ -43,7 +43,7 @@ static int lsmbus_recv_byte(device_t dev)
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return do_smbus_recv_byte(res->base, device);
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}
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static int lsmbus_send_byte(device_t dev, uint8_t val)
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static int lsmbus_send_byte(device_t dev, u8 val)
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{
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unsigned device;
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struct resource *res;
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@ -57,7 +57,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
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return do_smbus_send_byte(res->base, device, val);
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}
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static int lsmbus_read_byte(device_t dev, uint8_t address)
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static int lsmbus_read_byte(device_t dev, u8 address)
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{
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unsigned device;
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struct resource *res;
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@ -71,7 +71,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
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return do_smbus_read_byte(res->base, device, address);
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}
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static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
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static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
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{
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unsigned device;
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struct resource *res;
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@ -90,7 +90,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
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outb(0, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* Byte data recv */
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/* Byte data recv. */
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outb(0x05, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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@ -98,7 +98,7 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
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if (smbus_wait_until_done(smbus_io_base) < 0)
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return -3;
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/* Lose check */
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/* Lose check. */
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
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/* Read results of transaction. */
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@ -140,7 +140,7 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device,
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if (smbus_wait_until_done(smbus_io_base) < 0)
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return -3;
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/* Lose check */
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/* Lose check. */
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global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
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if (global_status_register != 0x80)
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@ -169,7 +169,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
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outb(address & 0xff, smbus_io_base + SMBHSTCMD);
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smbus_delay();
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/* Byte data read */
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/* Byte data read. */
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outb(0x07, smbus_io_base + SMBHSTPRTCL);
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smbus_delay();
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@ -177,7 +177,7 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device,
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if (smbus_wait_until_done(smbus_io_base) < 0)
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return -3;
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/* Lose check */
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/* Lose check. */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
/* Read results of transaction. */
|
||||
|
|
@ -219,7 +219,7 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device,
|
|||
if (smbus_wait_until_done(smbus_io_base) < 0)
|
||||
return -3;
|
||||
|
||||
/* Lose check */
|
||||
/* Lose check. */
|
||||
global_status_register = inb(smbus_io_base + SMBHSTSTAT) & 0x80;
|
||||
|
||||
if (global_status_register != 0x80)
|
||||
|
|
|
|||
|
|
@ -28,7 +28,10 @@
|
|||
static void usb1_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_nvidia_ck804_config const *conf = dev->chip_info;
|
||||
if (conf->usb1_hc_reset) {
|
||||
|
||||
if (!conf->usb1_hc_reset)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Somehow the warm reset does not really reset the USB
|
||||
* controller. Later, during boot, when the Bus Master bit is
|
||||
|
|
@ -36,13 +39,12 @@ static void usb1_init(struct device *dev)
|
|||
* misbehavior. Was detected on Sun Ultra40, where mptable
|
||||
* was damaged.
|
||||
*/
|
||||
uint32_t bar0 = pci_read_config32(dev, 0x10);
|
||||
uint32_t *regs = (uint32_t *) (bar0 & ~0xfff);
|
||||
u32 bar0 = pci_read_config32(dev, 0x10);
|
||||
u32 *regs = (u32 *) (bar0 & ~0xfff);
|
||||
|
||||
/* OHCI USB HCCommandStatus Register, HostControllerReset bit */
|
||||
regs[2] |= 1;
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
|
|
|
|||
|
|
@ -27,7 +27,8 @@
|
|||
|
||||
static void usb2_init(struct device *dev)
|
||||
{
|
||||
uint32_t dword;
|
||||
u32 dword;
|
||||
|
||||
dword = pci_read_config32(dev, 0xf8);
|
||||
dword |= 40;
|
||||
pci_write_config32(dev, 0xf8, dword);
|
||||
|
|
|
|||
Loading…
Reference in New Issue