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sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields 

Clang complains about this.

Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2022-02-18 14:21:45 +01:00 committed by Felix Held
parent cdad992f0f
commit 7e397ac4e7
2 changed files with 13 additions and 13 deletions
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14
src/southbridge/intel/i82801ix/chip.h
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@ -55,17 +55,17 @@ struct southbridge_intel_i82801ix_config {
/* IDE configuration */
uint8_t sata_port_map : 6;
int sata_clock_request : 1;
int sata_traffic_monitor : 1;
unsigned int sata_clock_request : 1;
unsigned int sata_traffic_monitor : 1;
int c4onc3_enable:1;
int c5_enable : 1;
int c6_enable : 1;
unsigned int c4onc3_enable:1;
unsigned int c5_enable : 1;
unsigned int c6_enable : 1;
int throttle_duty : 3;
unsigned int throttle_duty : 3;
/* Bit mask to tell whether a PCIe slot is implemented as slot. */
int pcie_slot_implemented : 6;
unsigned int pcie_slot_implemented : 6;
/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
struct {

12
src/southbridge/intel/i82801jx/chip.h
View File

@ -42,16 +42,16 @@ struct southbridge_intel_i82801jx_config {
/* IDE configuration */
uint8_t sata_port_map : 6;
int sata_clock_request : 1;
unsigned int sata_clock_request : 1;
int c4onc3_enable:1;
int c5_enable : 1;
int c6_enable : 1;
unsigned int c4onc3_enable:1;
unsigned int c5_enable : 1;
unsigned int c6_enable : 1;
int throttle_duty : 3;
unsigned int throttle_duty : 3;
/* Bit mask to tell whether a PCIe slot is implemented as slot. */
int pcie_slot_implemented : 6;
unsigned int pcie_slot_implemented : 6;
/* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
struct {