mb/asus/p5ql-em: Add mainboard
Tested, working: - First dimm slot of each channel - USB, SATA - CPU FSB at 800, 1067 and 1333MHz - Libgfxinit on DVI and VGA slot - PCI slot - Realtek NIC (configure MAC address in Kconfig) - PEG slot - PS2 keyboard Tested, not working: - second dimm slot for each channel. Those are hooked up to the second rank of the channel, instead of rank 3 and 4. The raminit does not support such setups. Untested: - PCIe x1 slot, likely works fine - HDMI Tested using SeaBIOS 1.12, Linux 4.19. Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
parent
b8df689a6a
commit
7e4bfe4b91
|
|
@ -0,0 +1,44 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
if BOARD_ASUS_P5QL_EM
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select ARCH_X86
|
||||
select CPU_INTEL_SOCKET_LGA775
|
||||
select NORTHBRIDGE_INTEL_X4X
|
||||
select SOUTHBRIDGE_INTEL_I82801JX
|
||||
select SUPERIO_WINBOND_W83627DHG
|
||||
select HAVE_ACPI_TABLES
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select HAVE_OPTION_TABLE
|
||||
select HAVE_CMOS_DEFAULT
|
||||
select HAVE_ACPI_RESUME
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
select MAINBOARD_HAS_LIBGFXINIT
|
||||
select REALTEK_8168_RESET
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default "asus/p5ql-em"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "P5QL-EM"
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 4
|
||||
|
||||
endif # BOARD_ASUS_P5QL_EM
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
config BOARD_ASUS_P5QL_EM
|
||||
bool "P5QL-EM"
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
romstage-y += gpio.c
|
||||
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
|
|
@ -0,0 +1 @@
|
|||
/* dummy */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/* This is board specific information:
|
||||
* IRQ routing for the 0:1e.0 PCI bridge of the ICH10
|
||||
*/
|
||||
|
||||
If (PICM) {
|
||||
Return (Package() {
|
||||
/* PCI slot */
|
||||
Package() { 0x0000ffff, 0, 0, 0x10},
|
||||
Package() { 0x0000ffff, 1, 0, 0x11},
|
||||
Package() { 0x0000ffff, 2, 0, 0x12},
|
||||
Package() { 0x0000ffff, 3, 0, 0x13},
|
||||
})
|
||||
} Else {
|
||||
Return (Package() {
|
||||
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
|
||||
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
|
||||
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
|
||||
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
|
||||
})
|
||||
}
|
||||
|
|
@ -0,0 +1 @@
|
|||
/* TODO */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <arch/acpigen.h>
|
||||
#include <southbridge/intel/i82801jx/nvs.h>
|
||||
|
||||
void acpi_create_gnvs(global_nvs_t *gnvs)
|
||||
{
|
||||
memset((void *)gnvs, 0, sizeof(*gnvs));
|
||||
|
||||
gnvs->pwrs = 1; /* Power state (AC = 1) */
|
||||
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
|
||||
gnvs->apic = 1; /* Enable APIC */
|
||||
gnvs->mpen = 1; /* Enable Multi Processing */
|
||||
gnvs->cmap = 0x01; /* Enable COM 1 port */
|
||||
}
|
||||
|
||||
/* TODO: Could work... */
|
||||
int get_cst_entries(acpi_cstate_t **entries)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
Category: desktop
|
||||
Board URL: https://www.asus.com/Motherboards/P5QLEM/
|
||||
ROM package: DIP-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
nmi=Enable
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
entries
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#390 5 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
395 4 e 6 debug_level
|
||||
|
||||
# coreboot config options: southbridge
|
||||
#408 1 e 0 unused
|
||||
409 2 e 7 power_on_after_fail
|
||||
411 1 e 1 nmi
|
||||
|
||||
# coreboot config options: cpu
|
||||
#424 8 r 0 unused
|
||||
|
||||
# coreboot config options: northbridge
|
||||
432 4 e 11 gfx_uma_size
|
||||
#436 548 r 0 unused
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
11 6 64M
|
||||
11 7 128M
|
||||
11 8 256M
|
||||
11 9 96M
|
||||
11 10 160M
|
||||
11 11 224M
|
||||
11 12 352M
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
Binary file not shown.
|
|
@ -0,0 +1,159 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
chip northbridge/intel/x4x # Northbridge
|
||||
device cpu_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_LGA775
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/model_1067x # CPU
|
||||
device lapic 0xACAC off end
|
||||
end
|
||||
end
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on # Host Bridge
|
||||
subsystemid 0x1043 0x8336
|
||||
end
|
||||
device pci 1.0 on # PEG
|
||||
subsystemid 0x1043 0x8336
|
||||
end
|
||||
device pci 2.0 on # Integrated graphics controller
|
||||
subsystemid 0x1043 0x8336
|
||||
end
|
||||
device pci 2.1 on # Integrated graphics controller 2
|
||||
subsystemid 0x1043 0x8336
|
||||
end
|
||||
device pci 3.0 off end # ME
|
||||
device pci 3.1 off end # ME
|
||||
device pci 3.2 off end # ME
|
||||
device pci 3.3 off end # ME
|
||||
chip southbridge/intel/i82801jx # Southbridge
|
||||
register "gpe0_en" = "0x40"
|
||||
|
||||
# Set AHCI mode.
|
||||
register "sata_port_map" = "0x3f"
|
||||
register "sata_clock_request" = "0"
|
||||
register "sata_traffic_monitor" = "0"
|
||||
|
||||
# Enable PCIe ports 0,1,3,4,5 as slots.
|
||||
register "pcie_slot_implemented" = "0x3b"
|
||||
|
||||
device pci 19.0 off end # GBE
|
||||
device pci 1a.0 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1a.1 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1a.2 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1a.7 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1b.0 on # Audio
|
||||
subsystemid 0x1043 0x82fe
|
||||
end
|
||||
device pci 1c.0 on end # PCIe 1 PCIe x1 Slot #1
|
||||
device pci 1c.1 on end # PCIe 2 PCIe x1 Slot #2
|
||||
device pci 1c.2 off end # PCIe 3
|
||||
device pci 1c.3 on # PCIe 4 1394 controller
|
||||
device pci 0.0 on
|
||||
subsystemid 0x1043 0x8313
|
||||
end
|
||||
end
|
||||
device pci 1c.4 on # PCIe 5 Marvell IDE
|
||||
device pci 0.0 on
|
||||
subsystemid 0x1043 0x82a2
|
||||
end
|
||||
end
|
||||
device pci 1c.5 on # PCIe 6 Realtek LAN
|
||||
device pci 0.0 on
|
||||
subsystemid 0x1043 0x82c6
|
||||
end
|
||||
end
|
||||
device pci 1d.0 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1d.1 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1d.2 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1d.7 on # USB
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1f.0 on # LPC bridge
|
||||
subsystemid 0x1043 0x82d4
|
||||
chip superio/winbond/w83627dhg
|
||||
device pnp 2e.0 on # Floppy
|
||||
# global
|
||||
irq 0x2c = 0x92
|
||||
#floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 0x06
|
||||
drq 0x74 = 0x02
|
||||
end
|
||||
device pnp 2e.1 on # Parallel port
|
||||
# parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off end # COM2, IR
|
||||
device pnp 2e.5 on # Keyboard, mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off end # SPI
|
||||
device pnp 2e.7 on end # GPIO6 (all input)
|
||||
device pnp 2e.8 off end # WDT0#, PLED
|
||||
device pnp 2e.9 off end # GPIO2
|
||||
device pnp 2e.109 on # GPIO3
|
||||
irq 0xf0 = 0xf3
|
||||
end
|
||||
device pnp 2e.209 on # GPIO4
|
||||
irq 0xf4 = 0x06
|
||||
end
|
||||
device pnp 2e.309 on # GPIO5
|
||||
irq 0xe0 = 0xdf
|
||||
irq 0xf3 = 0x09 # RSVD SUSLED settings
|
||||
end
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HWM, front panel LED
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.c off end # PECI, SST
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on # SATA
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1f.3 on # SMbus
|
||||
subsystemid 0x1043 0x82d4
|
||||
end
|
||||
device pci 1f.5 off end # SATA IDE mode
|
||||
device pci 1f.6 off end # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0 and up
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x00000001 // OEM revision
|
||||
)
|
||||
{
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/common/acpi/platform.asl>
|
||||
#include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/x4x/acpi/x4x.asl>
|
||||
#include <southbridge/intel/i82801jx/acpi/ich10.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
--
|
||||
-- This file is part of the coreboot project.
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1,
|
||||
HDMI2,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio10 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_GPIO,
|
||||
.gpio19 = GPIO_MODE_GPIO,
|
||||
.gpio20 = GPIO_MODE_GPIO,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio10 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio18 = GPIO_DIR_OUTPUT,
|
||||
.gpio19 = GPIO_DIR_INPUT,
|
||||
.gpio20 = GPIO_DIR_OUTPUT,
|
||||
.gpio21 = GPIO_DIR_OUTPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio12 = GPIO_LEVEL_LOW,
|
||||
.gpio18 = GPIO_LEVEL_HIGH,
|
||||
.gpio20 = GPIO_LEVEL_HIGH,
|
||||
.gpio21 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio27 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio7 = GPIO_INVERT,
|
||||
.gpio10 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio56 = GPIO_MODE_GPIO,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_OUTPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_OUTPUT,
|
||||
.gpio56 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio34 = GPIO_LEVEL_LOW,
|
||||
.gpio35 = GPIO_LEVEL_LOW,
|
||||
.gpio49 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0888,
|
||||
0x104382fe, // Subsystem ID
|
||||
13, // Number of entries
|
||||
|
||||
/* Pin Widget Verb Table */
|
||||
AZALIA_PIN_CFG(0, 0x11, 0x99430130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014010),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x01011012),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x01016011),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x01012014),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
|
||||
AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
|
||||
|
||||
/* HDMI audio */
|
||||
0x80862803,
|
||||
0x80860101,
|
||||
1,
|
||||
|
||||
AZALIA_PIN_CFG(1, 0x03, 0x18560010),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
|
||||
const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pnp_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <southbridge/intel/i82801jx/i82801jx.h>
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
#include <southbridge/intel/common/pmclib.h>
|
||||
#include <northbridge/intel/x4x/x4x.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <arch/romstage.h>
|
||||
#include <cf9_reset.h>
|
||||
#include <superio/winbond/w83627dhg/w83627dhg.h>
|
||||
#include <superio/winbond/common/winbond.h>
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
|
||||
#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
|
||||
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
|
||||
|
||||
static u8 msr_get_fsb(void)
|
||||
{
|
||||
u8 fsbcfg;
|
||||
msr_t msr;
|
||||
const u32 eax = cpuid_eax(1);
|
||||
|
||||
/* Netburst */
|
||||
if (((eax >> 8) & 0xf) == 0xf) {
|
||||
msr = rdmsr(MSR_EBC_FREQUENCY_ID);
|
||||
fsbcfg = (msr.lo >> 16) & 0x7;
|
||||
} else { /* Intel Core 2 */
|
||||
msr = rdmsr(MSR_FSB_FREQ);
|
||||
fsbcfg = msr.lo & 0x7;
|
||||
}
|
||||
|
||||
return fsbcfg;
|
||||
}
|
||||
|
||||
/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */
|
||||
static int setup_sio_gpio(void)
|
||||
{
|
||||
int need_reset = 0;
|
||||
u8 reg, old_reg;
|
||||
|
||||
u8 bsel = msr_get_fsb();
|
||||
switch (bsel) {
|
||||
case 0:
|
||||
case 2:
|
||||
case 4:
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_WARNING,
|
||||
"BSEL: Unsupported FSB frequency, using 800MHz\n");
|
||||
bsel = 2; /* 800MHz */
|
||||
break;
|
||||
}
|
||||
|
||||
pnp_enter_ext_func_mode(GPIO_DEV);
|
||||
pnp_set_logical_device(GPIO_DEV);
|
||||
|
||||
/*
|
||||
* P5QL-EM:
|
||||
* BSEL0 -> not hooked up (not supported anyways)
|
||||
* BSEL1 -> GPIO33 (inverted)
|
||||
* BSEL2 -> GPIO40
|
||||
*/
|
||||
reg = 0x92;
|
||||
/* Multi-function Pin Selection */
|
||||
old_reg = pnp_read_config(GPIO_DEV, 0x2c);
|
||||
pnp_write_config(GPIO_DEV, 0x2c, reg);
|
||||
need_reset = (reg != old_reg);
|
||||
|
||||
pnp_write_config(GPIO_DEV, 0x30, 0x0e); /* Enable GPIO3x,4x,5x */
|
||||
pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3x direction */
|
||||
pnp_write_config(GPIO_DEV, 0xf2, 0x08); /* GPIO3x inversion */
|
||||
pnp_write_config(GPIO_DEV, 0xf4, 0x06); /* GPIO4x direction */
|
||||
|
||||
const int gpio33 = (bsel & 2) >> 1;
|
||||
const int gpio40 = (bsel & 4) >> 2;
|
||||
reg = (gpio33 << 3);
|
||||
old_reg = pnp_read_config(GPIO_DEV, 0xf1); /* GPIO3x data */
|
||||
/* Set GPIO32 high like vendor firmware */
|
||||
pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg | 4);
|
||||
need_reset += ((reg & 0x8) != (old_reg & 0x8));
|
||||
|
||||
reg = gpio40;
|
||||
old_reg = pnp_read_config(GPIO_DEV, 0xf5); /* GPIO4x data */
|
||||
pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg);
|
||||
need_reset += ((reg & 0x1) != (old_reg & 0x1));
|
||||
pnp_exit_ext_func_mode(GPIO_DEV);
|
||||
|
||||
return need_reset;
|
||||
}
|
||||
|
||||
static void mb_gpio_init(void)
|
||||
{
|
||||
/* Set the value for GPIO base address register and enable GPIO. */
|
||||
pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1));
|
||||
pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10);
|
||||
|
||||
setup_pch_gpios(&mainboard_gpio_map);
|
||||
|
||||
/* Enable IOAPIC */
|
||||
RCBA8(0x31ff) = 0x03;
|
||||
RCBA8(0x31ff);
|
||||
}
|
||||
|
||||
static void ich10_enable_lpc(void)
|
||||
{
|
||||
/* Configure serial IRQs.*/
|
||||
pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
|
||||
pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF1_LPC_EN | KBC_LPC_EN
|
||||
| FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
|
||||
/* Hardware monitor IO range */
|
||||
pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x00000295);
|
||||
}
|
||||
|
||||
void mainboard_romstage_entry(void)
|
||||
{
|
||||
/* This board has first dimm slot of each channel hooked up to
|
||||
rank0 and rank1, while the second dimm slot is only connected
|
||||
to rank1. The raminit does not support such setups
|
||||
const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */
|
||||
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
|
||||
u8 boot_path = 0;
|
||||
u8 s3_resume;
|
||||
|
||||
/* Set southbridge and Super I/O GPIOs. */
|
||||
ich10_enable_lpc();
|
||||
mb_gpio_init();
|
||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
|
||||
console_init();
|
||||
|
||||
enable_smbus();
|
||||
|
||||
x4x_early_init();
|
||||
|
||||
s3_resume = southbridge_detect_s3_resume();
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
if (!s3_resume && setup_sio_gpio()) {
|
||||
printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n");
|
||||
full_reset();
|
||||
}
|
||||
|
||||
sdram_initialize(boot_path, spd_addrmap);
|
||||
|
||||
x4x_late_init(s3_resume);
|
||||
|
||||
printk(BIOS_DEBUG, "x4x late init complete\n");
|
||||
}
|
||||
Loading…
Reference in New Issue