mainboard/google/reef: Configure SDCARD card detect pin
This configures GPIO_177 as an input pin for SDCARD card detect. This also changes the ownership of the pin from ACPI to GPIO driver. Assign the sdcard card detect pin in devicetree for reef variants. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -17,6 +17,9 @@ chip soc/intel/apollolake
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# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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register "prt0_gpio" = "GPIO_122"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "GPIO_177"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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@ -59,7 +59,7 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */
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PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */
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/* Card detect is active LOW with external pull up. */
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PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */
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PAD_CFG_GPI_GPIO_DRIVER(GPIO_177, NONE, DEEP), /* SDCARD_CD_N */
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PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */
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/* CLK feedback, internal signal, needs 20K pull down */
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PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */
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@ -17,6 +17,9 @@ chip soc/intel/apollolake
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# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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register "prt0_gpio" = "GPIO_122"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "GPIO_177"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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@ -17,6 +17,9 @@ chip soc/intel/apollolake
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# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
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register "prt0_gpio" = "GPIO_122"
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# GPIO for SD card detect
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register "sdcard_cd_gpio" = "GPIO_177"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-22.3.
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# [14:8] steps of delay for HS400, each 125ps.
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