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intel/gma: Use defines for registers and values in edid.c 

This replaces magic values with defines without changing any value.

Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/16339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Sebastian "Swift Geek" Grzywna 2016-09-08 01:50:32 +02:00 committed by Nico Huber
parent e642b2d1d3
commit 7e516fbb47
1 changed files with 34 additions and 20 deletions
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54
src/drivers/intel/gma/edid.c
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@ -2,6 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com>
* Copyright (C) 2016 Sebastian Grzywna <swiftgeek@gmail.com>
* *
* This program is free software; you can redistribute it and/or * This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as * modify it under the terms of the GNU General Public License as
@ -20,13 +21,19 @@
#include "i915_reg.h" #include "i915_reg.h"
#include "edid.h" #include "edid.h"
#define GMBUS0_ADDR (mmio + 4 * 0)
#define GMBUS1_ADDR (mmio + 4 * 1)
#define GMBUS2_ADDR (mmio + 4 * 2)
#define GMBUS3_ADDR (mmio + 4 * 3)
#define GMBUS5_ADDR (mmio + 4 * 8)
#define AT24_ADDR 0x50 /* EDID EEPROM */
static void wait_rdy(u8 *mmio) static void wait_rdy(u8 *mmio)
{ {
unsigned try = 100; unsigned try = 100;
while (try--) { while (try--) {
if (read32(mmio + 8) & (1 << 11)) if (read32(GMBUS2_ADDR) & GMBUS_HW_RDY)
return; return;
udelay(10); udelay(10);
} }
@ -35,19 +42,22 @@ static void wait_rdy(u8 *mmio)
static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)
{ {
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 0, bus); write32(GMBUS0_ADDR, bus);
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 8, 0); write32(GMBUS5_ADDR, 0);
write32(mmio + 4 * 1, 0x4e0400a1); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
| GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT )
| GMBUS_SLAVE_READ | (AT24_ADDR << 1) );
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 8, 0); write32(GMBUS5_ADDR, 0);
write32(mmio + 4 * 1, 0x80000000); write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT);
write32(mmio + 4 * 1, 0x00000000); write32(GMBUS1_ADDR, 0);
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 1, 0x480000a0); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE
| (AT24_ADDR << 1) );
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 0, 0x48000000); write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
write32(mmio + 4 * 2, 0x00008000); write32(GMBUS2_ADDR, GMBUS_INUSE);
} }
void intel_gmbus_stop(u8 *mmio) void intel_gmbus_stop(u8 *mmio)
@ -65,30 +75,34 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
wait_rdy(mmio); wait_rdy(mmio);
/* 100 KHz, hold 0ns, */ /* 100 KHz, hold 0ns, */
write32(mmio + 4 * 0, bus); write32(GMBUS0_ADDR, bus);
wait_rdy(mmio); wait_rdy(mmio);
/* Ensure index bits are disabled. */ /* Ensure index bits are disabled. */
write32(mmio + 4 * 8, 0); write32(GMBUS5_ADDR, 0);
write32(mmio + 4 * 1, 0x46000000 | (slave << 1)); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
| (slave << 1) );
wait_rdy(mmio); wait_rdy(mmio);
/* Ensure index bits are disabled. */ /* Ensure index bits are disabled. */
write32(mmio + 4 * 8, 0); write32(GMBUS5_ADDR, 0);
write32(mmio + 4 * 1, 0x4a000001 | (slave << 1) write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT
| (edid_size << 16)); | GMBUS_CYCLE_STOP
| (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
for (i = 0; i < edid_size / 4; i++) { for (i = 0; i < edid_size / 4; i++) {
u32 reg32; u32 reg32;
wait_rdy(mmio); wait_rdy(mmio);
reg32 = read32(mmio + 4 * 3); reg32 = read32(GMBUS3_ADDR);
edid[4 * i] = reg32 & 0xff; edid[4 * i] = reg32 & 0xff;
edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff;
edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff;
edid[4 * i + 3] = (reg32 >> 24) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff;
} }
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 1, 0x4a800000 | (slave << 1)); write32(GMBUS1_ADDR, GMBUS_SW_RDY
| GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP
| (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
wait_rdy(mmio); wait_rdy(mmio);
write32(mmio + 4 * 0, 0x48000000); write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
write32(mmio + 4 * 2, 0x00008000); write32(GMBUS2_ADDR, GMBUS_INUSE);
printk (BIOS_SPEW, "EDID:\n"); printk (BIOS_SPEW, "EDID:\n");
for (i = 0; i < 128; i++) { for (i = 0; i < 128; i++) {