soc/intel/apollolake: Switch to snake case for SataPortsEnable

For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.

Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>

src/mainboard/intel/apollolake_rvp/devicetree.cb

@@ -21,8 +21,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 		end
 		device pci 13.0 on end	# - PCIe-A 0
 		device pci 13.2 on end	# - Onboard Lan

src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb

@@ -121,8 +121,8 @@ chip soc/intel/apollolake
 		device pci 0f.2 on  end # - Heci3
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 		end
 		device pci 13.0 off end	# - PCIe-A 0 Slot 1
 		device pci 13.1 off end	# - PCIe-A 1

src/mainboard/intel/leafhill/devicetree.cb

@@ -21,8 +21,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 		end
 		device pci 13.0 on end	# - PCIe-A 0
 		device pci 13.2 on end	# - Onboard Lan

src/mainboard/intel/minnow3/devicetree.cb

@@ -21,8 +21,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 		end
 		device pci 13.0 on end	# - PCIe-A 0
 		device pci 13.2 on end	# - Onboard Lan

src/mainboard/kontron/mal10/variants/mal10/devicetree.cb

@@ -19,8 +19,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end # TXE
 		device pci 11.0 off end # ISH
 		device pci 12.0 on	# SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 		end
 		device pci 13.0 on      # PCIe-A 1 (Root Port 2)
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"

src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb

@@ -69,8 +69,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0 - MACPHY

src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb

@@ -67,8 +67,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 			register "sata_ports_ssd[0]" = "1"
 			register "sata_ports_ssd[1]" = "1"
 			register "DisableSataSalpSupport" = "1"

src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb

@@ -64,8 +64,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb

@@ -58,8 +58,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb

@@ -67,8 +67,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 			register "sata_ports_ssd[0]" = "1"
 			register "sata_ports_ssd[1]" = "1"
 			register "DisableSataSalpSupport" = "1"

src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb

@@ -38,8 +38,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 			register "sata_ports_ssd[0]" = "1"
 			register "sata_ports_ssd[1]" = "1"
 			register "DisableSataSalpSupport" = "1"

src/mainboard/starlabs/lite/variants/glk/devicetree.cb

@@ -71,7 +71,7 @@ chip soc/intel/apollolake
 		device ref heci2	on  end
 		device ref heci3	on  end
 		device ref sata		on
-			register "SataPortsEnable[0]"	= "1"
+			register "sata_ports_enable[0]"	= "1"
 		end
 		device ref xhci		on
 			# Motherboard USB Type C

src/mainboard/starlabs/lite/variants/glkr/devicetree.cb

@@ -71,7 +71,7 @@ chip soc/intel/apollolake
 		device ref heci2	on  end
 		device ref heci3	on  end
 		device ref sata		on
-			register "SataPortsEnable[0]"	= "1"
+			register "sata_ports_enable[0]"	= "1"
 		end
 		device ref xhci		on
 			# Motherboard USB Type C

src/mainboard/up/squared/devicetree.cb

@@ -35,8 +35,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on end	# - TXE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 on	# - SATA
-			register "SataPortsEnable[0]" = "1"
-			register "SataPortsEnable[1]" = "1"
+			register "sata_ports_enable[0]" = "1"
+			register "sata_ports_enable[1]" = "1"
 		end
 		device pci 13.0 on end	# - PCIe-A 1 - PcieRootPort[2]
 		device pci 13.1 on end  # - PCIe-A 2 - PcieRootPort[3]

src/soc/intel/apollolake/chip.c

@@ -737,7 +737,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	if (is_devfn_enabled(PCH_DEVFN_SATA)) {
 		silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport);
 		silconfig->SpeedLimit = cfg->sata_speed;
-		memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable,
+		memcpy(silconfig->SataPortsEnable, cfg->sata_ports_enable,
 			sizeof(silconfig->SataPortsEnable));
 		memcpy(silconfig->SataPortsSolidStateDrive, cfg->sata_ports_ssd,
 			sizeof(silconfig->SataPortsSolidStateDrive));

src/soc/intel/apollolake/chip.h

@@ -107,7 +107,7 @@ struct soc_intel_apollolake_config {
 	uint8_t SataPortsHotPlug[2];
 
 	/* Sata Ports Enable */
-	uint8_t SataPortsEnable[2];
+	uint8_t sata_ports_enable[2];
 
 	/* Sata Ports Solid State Drive */
 	uint8_t sata_ports_ssd[2];