Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-37
Creator: Li-Ta Lo <ollie@lanl.gov> TLA is really diffcult to use. How am I going to roll back my last commit ? git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
parent
acfaeceffd
commit
7e5fbd6fc0
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "vt8231.h"
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static void acpi_init(struct device *dev)
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{
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printk_debug("Configuring VIA ACPI\n");
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// Set ACPI base address to IO 0x4000
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pci_write_config32(dev, 0x48, 0x4001);
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// Enable ACPI access (and setup like award)
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pci_write_config8(dev, 0x41, 0x84);
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// Set hardware monitor base address to IO 0x6000
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pci_write_config32(dev, 0x70, 0x6001);
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// Enable hardware monitor (and setup like award)
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pci_write_config8(dev, 0x74, 0x01);
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// set IO base address to 0x5000
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pci_write_config32(dev, 0x90, 0x5001);
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// Enable SMBus
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pci_write_config8(dev, 0xd2, 0x01);
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}
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static struct device_operations acpi_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = acpi_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &acpi_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_8231_4,
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};
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "vt8231.h"
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#include "chip.h"
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static void ide_init(struct device *dev)
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{
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struct southbridge_via_vt8231_config *conf;
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unsigned char enables;
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if (!conf->enable_native_ide) {
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// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
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// interrupts. Using PCI ints confuses linux for some reason.
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printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
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enables = pci_read_config8(dev, 0x42);
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printk_debug("enables in reg 0x42 0x%x\n", enables);
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enables &= ~0xc0; // compatability mode
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pci_write_config8(dev, 0x42, enables);
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enables = pci_read_config8(dev, 0x42);
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printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
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}
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enables = pci_read_config8(dev, 0x40);
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printk_debug("enables in reg 0x40 0x%x\n", enables);
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enables |= 3;
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pci_write_config8(dev, 0x40, enables);
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enables = pci_read_config8(dev, 0x40);
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printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
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// Enable prefetch buffers
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enables = pci_read_config8(dev, 0x41);
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enables |= 0xf0;
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pci_write_config8(dev, 0x41, enables);
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// Lower thresholds (cause award does it)
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enables = pci_read_config8(dev, 0x43);
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enables &= ~0x0f;
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enables |= 0x05;
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pci_write_config8(dev, 0x43, enables);
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// PIO read prefetch counter (cause award does it)
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pci_write_config8(dev, 0x44, 0x18);
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// Use memory read multiple
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pci_write_config8(dev, 0x45, 0x1c);
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// address decoding.
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// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
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// kevinh@ispiri.com - the standard linux drivers seem ass slow when
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// used in native mode - I've changed back to classic
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enables = pci_read_config8(dev, 0x9);
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printk_debug("enables in reg 0x9 0x%x\n", enables);
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// by the book, set the low-order nibble to 0xa.
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if (conf->enable_native_ide) {
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enables &= ~0xf;
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// cf/cg silicon needs an 'f' here.
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enables |= 0xf;
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} else {
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enables &= ~0x5;
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}
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pci_write_config8(dev, 0x9, enables);
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enables = pci_read_config8(dev, 0x9);
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printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
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// standard bios sets master bit.
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enables = pci_read_config8(dev, 0x4);
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printk_debug("command in reg 0x4 0x%x\n", enables);
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enables |= 7;
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// No need for stepping - kevinh@ispiri.com
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enables &= ~0x80;
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pci_write_config8(dev, 0x4, enables);
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enables = pci_read_config8(dev, 0x4);
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printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
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if (!conf->enable_native_ide) {
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// Use compatability mode - per award bios
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pci_write_config32(dev, 0x10, 0x0);
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pci_write_config32(dev, 0x14, 0x0);
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pci_write_config32(dev, 0x18, 0x0);
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pci_write_config32(dev, 0x1c, 0x0);
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// Force interrupts to use compat mode - just like Award bios
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pci_write_config8(dev, 0x3d, 00);
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pci_write_config8(dev, 0x3c, 0xff);
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}
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_82C586_1,
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};
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include <pc80/mc146818rtc.h>
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#include "vt8231.h"
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#include "chip.h"
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/* PIRQ init
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*/
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void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
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static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
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/*
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Our IDSEL mappings are as follows
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PCI slot is AD31 (device 15) (00:14.0)
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Southbridge is AD28 (device 12) (00:11.0)
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*/
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static void pci_routing_fixup(struct device *dev)
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{
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printk_info("%s: dev is %p\n", __FUNCTION__, dev);
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if (dev) {
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/* initialize PCI interupts - these assignments depend
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on the PCB routing of PINTA-D
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PINTA = IRQ11
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PINTB = IRQ5
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PINTC = IRQ10
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PINTD = IRQ12
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*/
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pci_write_config8(dev, 0x55, 0xb0);
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pci_write_config8(dev, 0x56, 0xa5);
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pci_write_config8(dev, 0x57, 0xc0);
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}
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// Standard southbridge components
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printk_info("setting southbridge\n");
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pci_assign_irqs(0, 0x11, southbridgeIrqs);
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// Ethernet built into southbridge
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printk_info("setting ethernet\n");
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pci_assign_irqs(0, 0x12, enetIrqs);
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// PCI slot
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x14, slotIrqs);
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printk_info("%s: DONE\n", __FUNCTION__);
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}
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static void vt8231_init(struct device *dev)
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{
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unsigned char enables;
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struct southbridge_via_vt8231_config *conf = dev->chip_info;
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printk_debug("vt8231 init\n");
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// enable the internal I/O decode
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enables = pci_read_config8(dev, 0x6C);
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enables |= 0x80;
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pci_write_config8(dev, 0x6C, enables);
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// Map 4MB of FLASH into the address space
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pci_write_config8(dev, 0x41, 0x7f);
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// Set bit 6 of 0x40, because Award does it (IO recovery time)
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// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
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// interrupts can be properly marked as level triggered.
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enables = pci_read_config8(dev, 0x40);
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pci_write_config8(dev, 0x40, enables);
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// Set 0x42 to 0xf0 to match Award bios
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enables = pci_read_config8(dev, 0x42);
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enables |= 0xf0;
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pci_write_config8(dev, 0x42, enables);
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// Set bit 3 of 0x4a, to match award (dummy pci request)
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enables = pci_read_config8(dev, 0x4a);
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enables |= 0x08;
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pci_write_config8(dev, 0x4a, enables);
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// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
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enables = pci_read_config8(dev, 0x4f);
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enables |= 0x08;
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pci_write_config8(dev, 0x4f, enables);
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// Set 0x58 to 0x03 to match Award
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pci_write_config8(dev, 0x58, 0x03);
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// enable the ethernet/RTC
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if (dev) {
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enables = pci_read_config8(dev, 0x51);
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enables |= 0x18;
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pci_write_config8(dev, 0x51, enables);
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}
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// enable IDE, since Linux won't do it.
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// First do some more things to devfn (17,0)
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// note: this should already be cleared, according to the book.
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enables = pci_read_config8(dev, 0x50);
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printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
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enables &= ~8; // need manifest constant here!
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printk_debug("set IDE reg. 50 to 0x%x\n", enables);
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pci_write_config8(dev, 0x50, enables);
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// set default interrupt values (IDE)
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enables = pci_read_config8(dev, 0x4c);
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printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
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// clear out whatever was there.
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enables &= ~0xf;
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enables |= 4;
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printk_debug("setting reg. 4c to 0x%x\n", enables);
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pci_write_config8(dev, 0x4c, enables);
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// set up the serial port interrupts.
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// com2 to 3, com1 to 4
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pci_write_config8(dev, 0x46, 0x04);
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pci_write_config8(dev, 0x47, 0x03);
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pci_write_config8(dev, 0x6e, 0x98);
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/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
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pci_write_config8(dev, 0x40, 0x54);
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//ethernet_fixup();
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// Start the rtc
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rtc_init(0);
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}
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static void southbridge_init(struct device *dev)
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{
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vt8231_init(dev);
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pci_routing_fixup(dev);
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}
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static struct device_operations vt8231_lpc_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = &southbridge_init,
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.scan_bus = scan_static_bus,
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.enable = 0,
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.ops_pci = 0,
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};
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static struct pci_driver lpc_driver __pci_driver = {
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.ops = &vt8231_lpc_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_8231,
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};
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "vt8231.h"
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/*
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* Enable the ethernet device and turn off stepping (because it is integrated
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* inside the southbridge)
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*/
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static void nic_init(struct device *dev)
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{
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uint8_t byte;
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printk_debug("Configuring VIA LAN\n");
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/* We don't need stepping - though the device supports it */
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byte = pci_read_config8(dev, PCI_COMMAND);
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byte &= ~PCI_COMMAND_WAIT;
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pci_write_config8(dev, PCI_COMMAND, byte);
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}
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static struct device_operations nic_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = nic_init,
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.enable = 0,
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.ops_pci = 0,
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};
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static struct pci_driver northbridge_driver __pci_driver = {
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.ops = &nic_ops,
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.vendor = PCI_VENDOR_ID_VIA,
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.device = PCI_DEVICE_ID_VIA_8233_7,
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};
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static void usb_on(int enable)
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{
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unsigned char regval;
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/* Base 8231 controller */
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device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
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/* USB controller 1 */
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device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
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/* USB controller 2 */
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device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
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/* enable USB1 */
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if(dev2) {
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if (enable) {
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pci_write_config8(dev2, 0x3c, 0x05);
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pci_write_config8(dev2, 0x04, 0x07);
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} else {
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pci_write_config8(dev2, 0x3c, 0x00);
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pci_write_config8(dev2, 0x04, 0x00);
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}
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}
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if(dev0) {
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regval = pci_read_config8(dev0, 0x50);
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if (enable)
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regval &= ~(0x10);
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else
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regval |= 0x10;
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pci_write_config8(dev0, 0x50, regval);
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}
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/* enable USB2 */
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if(dev3) {
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if (enable) {
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pci_write_config8(dev3, 0x3c, 0x05);
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pci_write_config8(dev3, 0x04, 0x07);
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} else {
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pci_write_config8(dev3, 0x3c, 0x00);
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pci_write_config8(dev3, 0x04, 0x00);
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}
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}
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if(dev0) {
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regval = pci_read_config8(dev0, 0x50);
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if (enable)
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regval &= ~(0x20);
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else
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regval |= 0x20;
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pci_write_config8(dev0, 0x50, regval);
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}
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}
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