GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/common/pmutil: Add dump_all_status() 

Change-Id: I10582941afd68425603f6c4cadd228797cd098e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2020-06-14 12:23:04 +03:00 committed by Angel Pons
parent f71f3ae9c2
commit 7e75f33de5
3 changed files with 26 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/southbridge/intel/common/pmutil.c
View File

@ -215,3 +215,12 @@ u16 reset_alt_gp_smi_status(void)
return reg16;
}
void dump_all_status(void)
{
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
dump_gpe0_status(reset_gpe0_status());
dump_alt_gp_smi_status(reset_alt_gp_smi_status());
dump_tco_status(reset_tco_status());
}

2
src/southbridge/intel/common/pmutil.h
View File

@ -125,6 +125,8 @@ void alt_gpi_mask(u16 clr, u16 set);
void smi_set_eos(void);
void dump_alt_gp_smi_status(u16 alt_gp_smi_sts);
u16 reset_alt_gp_smi_status(void);
void dump_all_status(void);
void southbridge_smm_xhci_sleep(u8 slp_type);
void gpi_route_interrupt(u8 gpi, u8 mode);
void southbridge_gate_memory_reset(void);

41
src/southbridge/intel/common/smi.c
View File

@ -17,31 +17,30 @@ u16 get_pmbase(void)
return lpc_get_pmbase();
}
static void smm_southbridge_enable(uint16_t pm1_events)
static int smi_enabled(void)
{
u32 smi_en;
u32 gpe0_en;
if (CONFIG(ELOG))
/* Log events from chipset before clearing */
if (CONFIG(ELOG))
pch_log_state();
printk(BIOS_DEBUG, "Initializing southbridge SMI...");
printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", lpc_get_pmbase());
smi_en = read_pmbase32(SMI_EN);
if (smi_en & APMC_EN) {
printk(BIOS_INFO, "SMI# handler already enabled?\n");
return;
return 1;
}
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
dump_gpe0_status(reset_gpe0_status());
dump_alt_gp_smi_status(reset_alt_gp_smi_status());
dump_tco_status(reset_tco_status());
return 0;
}
static void smm_southbridge_enable(uint16_t pm1_events)
{
u32 smi_en;
u32 gpe0_en;
/* Disable GPE0 PME_B0 */
gpe0_en = read_pmbase32(GPE0_EN);
@ -73,6 +72,10 @@ static void smm_southbridge_enable(uint16_t pm1_events)
void global_smi_enable(void)
{
if (smi_enabled())
return;
dump_all_status();
smm_southbridge_enable(PWRBTN_EN | GBL_EN);
}
@ -97,22 +100,8 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
void smm_southbridge_clear_state(void)
{
u32 smi_en;
if (CONFIG(ELOG))
/* Log events from chipset before clearing */
pch_log_state();
printk(BIOS_DEBUG, "Initializing Southbridge SMI...\n");
printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
smi_en = inl(get_pmbase() + SMI_EN);
if (smi_en & APMC_EN) {
printk(BIOS_INFO, "SMI# handler already enabled?\n");
if (smi_enabled())
return;
}
printk(BIOS_DEBUG, "\n");
/* Dump and clear status registers */
reset_smi_status();