soc/intel: Add skeleton infrastructure for Apollolake SOC
This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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config SOC_INTEL_APOLLOLAKE
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bool
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help
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Intel Apollolake support
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if SOC_INTEL_APOLLOLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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# CPU specific options
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select IOAPIC
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select SMP
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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# Misc options
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select COLLECT_TIMESTAMPS
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select HAVE_INTEL_FIRMWARE
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select PARALLEL_MP
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select REG_SCRIPT
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select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
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select SOC_INTEL_COMMON
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select UDELAY_TSC
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config CPU_ADDR_BITS
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int
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default 36
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endif
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ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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romstage-y += placeholders.c
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smm-y += placeholders.c
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ramstage-y += placeholders.c
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endif
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#include <cbmem.h>
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#include <cpu/x86/smm.h>
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void *cbmem_top(void)
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{
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return NULL;
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}
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void southbridge_smi_set_eos(void)
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{
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}
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