soc/intel: Add skeleton infrastructure for Apollolake SOC

This is the very very minimum needed to compile the code.

Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13297
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Alexandru Gagniuc 2015-10-06 10:33:49 -07:00 committed by Stefan Reinauer
parent 6be6c8f282
commit 7e86cd4bb2
3 changed files with 64 additions and 0 deletions

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config SOC_INTEL_APOLLOLAKE
bool
help
Intel Apollolake support
if SOC_INTEL_APOLLOLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
# CPU specific options
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select IOAPIC
select SMP
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
# Misc options
select COLLECT_TIMESTAMPS
select HAVE_INTEL_FIRMWARE
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select PARALLEL_MP
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select PCIEXP_CLK_PM
select PCIEXP_L1_SUB_STATE
select REG_SCRIPT
select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
select SOC_INTEL_COMMON
select UDELAY_TSC
config CPU_ADDR_BITS
int
default 36
endif

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ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y)
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
romstage-y += placeholders.c
smm-y += placeholders.c
ramstage-y += placeholders.c
endif

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#include <cbmem.h>
#include <cpu/x86/smm.h>
void *cbmem_top(void)
{
return NULL;
}
void southbridge_smi_set_eos(void)
{
}