soc/intel/common/gpio: Rework PAD config macro to add lock support
This patch extends `struct pad_config` to add new variable for gpio lock action. Additionally, it creates new GPIO PAD configuration macros that perform GPIO pad configuration and pad lock configuration as well. List of new macros are: 1. PAD_CFG_NF_LOCK 2. PAD_CFG_GPO_LOCK 3. PAD_CFG_GPI_LOCK 4. PAD_CFG_GPI_TRIG_OWN_LOCK 5. PAD_CFG_GPI_GPIO_DRIVER_LOCK 6. PAD_CFG_GPI_INT_LOCK 7. PAD_CFG_GPI_APIC_LOCK 8. PAD_CFG_GPI_IRQ_WAKE_LOCK Mainboard users can use the above macros to lock the PAD after configuration. So far on IA chipset, the default GPIO pad lock configuration reset type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603) to configure the GPP PAD reset type the same as lock configuration reset type to avoid GPP reset value misconfiguration issue. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Subrata Banik
parent
fe678cbd19
commit
7e8a0e61e7
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@ -345,6 +345,8 @@ static void gpio_configure_pad(const struct pad_config *cfg)
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gpio_configure_owner(cfg, comm);
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gpi_enable_smi(cfg, comm);
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gpi_enable_nmi(cfg, comm);
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if (cfg->lock_action)
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gpio_lock_pad(cfg->pad, cfg->lock_action);
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}
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void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
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@ -468,13 +470,13 @@ gpio_pad_config_lock_using_sbi(const struct gpio_lock_config *pad_info,
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.fid = 0,
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};
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if (!(pad_info->action & GPIO_LOCK_FULL)) {
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printk(BIOS_ERR, "%s: Error: no action specified for pad %d!\n",
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if (!(pad_info->lock_action & GPIO_LOCK_FULL)) {
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printk(BIOS_ERR, "%s: Error: no lock_action specified for pad %d!\n",
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__func__, pad_info->pad);
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return;
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}
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if ((pad_info->action & GPIO_LOCK_CONFIG) == GPIO_LOCK_CONFIG) {
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if ((pad_info->lock_action & GPIO_LOCK_CONFIG) == GPIO_LOCK_CONFIG) {
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if (CONFIG(DEBUG_GPIO))
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printk(BIOS_INFO, "%s: Locking pad %d configuration\n",
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__func__, pad_info->pad);
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@ -484,7 +486,7 @@ gpio_pad_config_lock_using_sbi(const struct gpio_lock_config *pad_info,
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printk(BIOS_ERR, "Failed to lock GPIO PAD, response = %d\n", response);
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}
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if ((pad_info->action & GPIO_LOCK_TX) == GPIO_LOCK_TX) {
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if ((pad_info->lock_action & GPIO_LOCK_TX) == GPIO_LOCK_TX) {
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if (CONFIG(DEBUG_GPIO))
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printk(BIOS_INFO, "%s: Locking pad %d Tx state\n",
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__func__, pad_info->pad);
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@ -552,14 +554,14 @@ static void
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gpio_pad_config_lock_using_pcr(const struct gpio_lock_config *pad_info,
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uint8_t pid, uint16_t offset, const uint32_t bit_mask)
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{
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if ((pad_info->action & GPIO_LOCK_CONFIG) == GPIO_LOCK_CONFIG) {
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if ((pad_info->lock_action & GPIO_LOCK_CONFIG) == GPIO_LOCK_CONFIG) {
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if (CONFIG(DEBUG_GPIO))
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printk(BIOS_INFO, "%s: Locking pad %d configuration\n",
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__func__, pad_info->pad);
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pcr_or32(pid, offset, bit_mask);
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}
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if ((pad_info->action & GPIO_LOCK_TX) == GPIO_LOCK_TX) {
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if ((pad_info->lock_action & GPIO_LOCK_TX) == GPIO_LOCK_TX) {
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if (CONFIG(DEBUG_GPIO))
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printk(BIOS_INFO, "%s: Locking pad %d TX state\n",
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__func__, pad_info->pad);
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@ -612,7 +614,7 @@ static int gpio_non_smm_lock_pad(const struct gpio_lock_config *pad_info)
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return 0;
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}
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int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action)
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int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action lock_action)
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{
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/* Skip locking GPIO PAD in early stages */
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if (ENV_ROMSTAGE_OR_BEFORE)
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@ -620,7 +622,7 @@ int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action)
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const struct gpio_lock_config pads = {
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.pad = pad,
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.action = action
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.lock_action = lock_action
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};
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if (!ENV_SMM && !CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS))
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@ -65,10 +65,18 @@
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typedef uint32_t gpio_t;
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enum gpio_lock_action {
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GPIO_UNLOCK = 0x0,
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GPIO_LOCK_CONFIG = 0x1,
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GPIO_LOCK_TX = 0x2,
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GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX,
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};
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struct pad_config {
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gpio_t pad;/* offset of pad within community */
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uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];/*
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Pad config data corresponding to DW0, DW1,.... */
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enum gpio_lock_action lock_action; /* Pad lock configuration */
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};
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/*
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@ -199,15 +207,9 @@ void gpio_configure_pads_with_override(const struct pad_config *base_cfg,
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*/
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void *gpio_dwx_address(const gpio_t pad);
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enum gpio_lock_action {
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GPIO_LOCK_CONFIG = 0x1,
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GPIO_LOCK_TX = 0x2,
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GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX,
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};
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struct gpio_lock_config {
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gpio_t pad;
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enum gpio_lock_action action;
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enum gpio_lock_action lock_action;
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};
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/*
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@ -227,14 +229,14 @@ struct gpio_lock_config {
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* function may only be called in SMM.
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*
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* @param pad: GPIO pad number
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* @param action: Which register to lock.
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* @param lock_action: Which register to lock.
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* @return 0 if successful,
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* 1 - unsuccessful
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* 2 - powered down
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* 3 - multi-cast mixed
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* -1 - sideband message failed or other error
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*/
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int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action action);
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int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action lock_action);
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/*
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* gpio_lock_pads() can be used to lock an array of gpio pads, avoiding
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@ -3,6 +3,8 @@
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#ifndef _SOC_BLOCK_GPIO_DEFS_H_
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#define _SOC_BLOCK_GPIO_DEFS_H_
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#include <intelblocks/gpio.h>
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#define PAD_CFG0_TX_STATE_BIT 0
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#define PAD_CFG0_TX_STATE (1 << PAD_CFG0_TX_STATE_BIT)
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#define PAD_CFG0_RX_STATE_BIT 1
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@ -129,6 +131,7 @@
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#define PAD_IRQ_ROUTE(value) PAD_CFG0_ROUTE_##value
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#define PAD_TRIG(value) PAD_CFG0_TRIG_##value
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#define PAD_PULL(value) PAD_CFG1_PULL_##value
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#define PAD_LOCK(value) GPIO_##value
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/* Disable the input/output buffer of the pad */
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#define PAD_CFG0_BUF_NO_DISABLE (0)
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@ -165,6 +168,15 @@
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.pad = __pad, \
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.pad_config[0] = __config0, \
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.pad_config[1] = __config1, \
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.lock_action = PAD_LOCK(UNLOCK), \
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}
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#define _PAD_CFG_STRUCT_LOCK(__pad, __config0, __config1, __action) \
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{ \
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.pad = __pad, \
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.pad_config[0] = __config0, \
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.pad_config[1] = __config1, \
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.lock_action = __action, \
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}
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#if GPIO_NUM_PAD_CFG_REGS > 2
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@ -174,6 +186,7 @@
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.pad_config[0] = __config0, \
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.pad_config[1] = __config1, \
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.pad_config[2] = __config2, \
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.lock_action = PAD_LOCK(UNLOCK), \
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}
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#else
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#define _PAD_CFG_STRUCT_3(__pad, __config0, __config1, __config2) \
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@ -186,6 +199,13 @@
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PAD_RESET(rst) | PAD_FUNC(func), \
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PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE))
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/* Native function configuration with lock */
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#define PAD_CFG_NF_LOCK(pad, pull, func, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_RESET(PWROK) | PAD_FUNC(func), \
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PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE), \
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PAD_LOCK(lock_action))
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#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL)
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/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S
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Not applicable to all SOCs. Refer EDS
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@ -230,6 +250,14 @@
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PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
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PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE))
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/* General purpose output with lock, no pullup/down. */
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#define PAD_CFG_GPO_LOCK(pad, val, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \
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PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \
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PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \
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PAD_LOCK(lock_action))
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/* General purpose output, with termination specified */
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#define PAD_CFG_TERM_GPO(pad, val, pull, rst) \
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_PAD_CFG_STRUCT(pad, \
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@ -258,6 +286,13 @@
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \
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PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
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/* General purpose input with lock */
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#define PAD_CFG_GPI_LOCK(pad, pull, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE), \
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PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \
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PAD_LOCK(lock_action))
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#define PAD_CFG_GPI_TRIG_IOSSTATE_OWN(pad, pull, rst, trig, iosstate, own) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | PAD_BUF(TX_DISABLE), \
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@ -279,12 +314,25 @@
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PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \
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PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own))
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#define PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, rst, trig, own, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | \
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PAD_TRIG(trig) | PAD_RX_POL(NONE) | PAD_BUF(TX_DISABLE), \
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PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own), PAD_LOCK(lock_action))
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#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | \
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PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \
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PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE))
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#define PAD_CFG_GPI_GPIO_DRIVER_LOCK(pad, pull, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(PWROK) | \
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PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), \
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PAD_PULL(pull) | PAD_CFG_OWN_GPIO(DRIVER) | PAD_IOSSTATE(TxDRxE), \
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PAD_LOCK(lock_action))
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#define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \
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@ -300,6 +348,10 @@
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#define PAD_CFG_GPI_INT(pad, pull, rst, trig) \
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PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, DRIVER)
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/* GPIO Interrupt with lock */
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#define PAD_CFG_GPI_INT_LOCK(pad, pull, trig, lock_action) \
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PAD_CFG_GPI_TRIG_OWN_LOCK(pad, pull, PWROK, trig, DRIVER, lock_action)
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/*
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* No Connect configuration for unconnected or unused pad.
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* Both TX and RX are disabled. RX disabling is done to avoid unnecessary
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@ -319,6 +371,14 @@
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PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
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PAD_IOSSTATE(TxDRxE))
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/* General purpose input with lock, routed to APIC */
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#define PAD_CFG_GPI_APIC_LOCK(pad, pull, trig, inv, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_BUF(TX_DISABLE) | \
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PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \
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PAD_IOSSTATE(TxDRxE), \
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PAD_LOCK(lock_action))
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/* General purpose input, routed to APIC - with IOStandby Config*/
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#define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \
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_PAD_CFG_STRUCT(pad, \
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@ -406,9 +466,19 @@
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PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
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PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE))
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#define PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, rst, trig, inv, route1, route2, lock_action) \
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_PAD_CFG_STRUCT_LOCK(pad, \
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PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \
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PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \
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PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE), \
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PAD_LOCK(lock_action))
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#define PAD_CFG_GPI_IRQ_WAKE(pad, pull, rst, trig, inv) \
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PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, IOAPIC, SCI)
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#define PAD_CFG_GPI_IRQ_WAKE_LOCK(pad, pull, trig, inv, lock_action) \
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PAD_CFG_GPI_DUAL_ROUTE_LOCK(pad, pull, PWROK, trig, inv, IOAPIC, SCI, lock_action)
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#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT */
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#endif /* _SOC_BLOCK_GPIO_DEFS_H_ */
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